1 /** 2 * dwc3-omap.c - OMAP Specific Glue layer 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/dwc3-omap.c) and ported 10 * to uboot. 11 * 12 * commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete() 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/slab.h> 20 #include <linux/interrupt.h> 21 #include <linux/platform_device.h> 22 #include <linux/platform_data/dwc3-omap.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/ioport.h> 26 #include <linux/io.h> 27 #include <linux/of.h> 28 #include <linux/of_platform.h> 29 #include <linux/extcon.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <linux/usb/otg.h> 33 34 /* 35 * All these registers belong to OMAP's Wrapper around the 36 * DesignWare USB3 Core. 37 */ 38 39 #define USBOTGSS_REVISION 0x0000 40 #define USBOTGSS_SYSCONFIG 0x0010 41 #define USBOTGSS_IRQ_EOI 0x0020 42 #define USBOTGSS_EOI_OFFSET 0x0008 43 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 44 #define USBOTGSS_IRQSTATUS_0 0x0028 45 #define USBOTGSS_IRQENABLE_SET_0 0x002c 46 #define USBOTGSS_IRQENABLE_CLR_0 0x0030 47 #define USBOTGSS_IRQ0_OFFSET 0x0004 48 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030 49 #define USBOTGSS_IRQSTATUS_1 0x0034 50 #define USBOTGSS_IRQENABLE_SET_1 0x0038 51 #define USBOTGSS_IRQENABLE_CLR_1 0x003c 52 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040 53 #define USBOTGSS_IRQSTATUS_2 0x0044 54 #define USBOTGSS_IRQENABLE_SET_2 0x0048 55 #define USBOTGSS_IRQENABLE_CLR_2 0x004c 56 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050 57 #define USBOTGSS_IRQSTATUS_3 0x0054 58 #define USBOTGSS_IRQENABLE_SET_3 0x0058 59 #define USBOTGSS_IRQENABLE_CLR_3 0x005c 60 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030 61 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034 62 #define USBOTGSS_IRQSTATUS_MISC 0x0038 63 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c 64 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040 65 #define USBOTGSS_IRQMISC_OFFSET 0x03fc 66 #define USBOTGSS_UTMI_OTG_CTRL 0x0080 67 #define USBOTGSS_UTMI_OTG_STATUS 0x0084 68 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480 69 #define USBOTGSS_TXFIFO_DEPTH 0x0508 70 #define USBOTGSS_RXFIFO_DEPTH 0x050c 71 #define USBOTGSS_MMRAM_OFFSET 0x0100 72 #define USBOTGSS_FLADJ 0x0104 73 #define USBOTGSS_DEBUG_CFG 0x0108 74 #define USBOTGSS_DEBUG_DATA 0x010c 75 #define USBOTGSS_DEV_EBC_EN 0x0110 76 #define USBOTGSS_DEBUG_OFFSET 0x0600 77 78 /* SYSCONFIG REGISTER */ 79 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) 80 81 /* IRQ_EOI REGISTER */ 82 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) 83 84 /* IRQS0 BITS */ 85 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) 86 87 /* IRQMISC BITS */ 88 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17) 89 #define USBOTGSS_IRQMISC_OEVT (1 << 16) 90 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13) 91 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12) 92 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11) 93 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8) 94 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5) 95 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4) 96 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3) 97 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0) 98 99 /* UTMI_OTG_CTRL REGISTER */ 100 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5) 101 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4) 102 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3) 103 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0) 104 105 /* UTMI_OTG_STATUS REGISTER */ 106 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31) 107 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9) 108 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8) 109 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4) 110 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3) 111 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2) 112 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1) 113 114 struct dwc3_omap { 115 struct device *dev; 116 117 int irq; 118 void __iomem *base; 119 120 u32 utmi_otg_status; 121 u32 utmi_otg_offset; 122 u32 irqmisc_offset; 123 u32 irq_eoi_offset; 124 u32 debug_offset; 125 u32 irq0_offset; 126 127 u32 dma_status:1; 128 129 struct extcon_specific_cable_nb extcon_vbus_dev; 130 struct extcon_specific_cable_nb extcon_id_dev; 131 struct notifier_block vbus_nb; 132 struct notifier_block id_nb; 133 134 struct regulator *vbus_reg; 135 }; 136 137 enum omap_dwc3_vbus_id_status { 138 OMAP_DWC3_ID_FLOAT, 139 OMAP_DWC3_ID_GROUND, 140 OMAP_DWC3_VBUS_OFF, 141 OMAP_DWC3_VBUS_VALID, 142 }; 143 144 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) 145 { 146 return readl(base + offset); 147 } 148 149 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) 150 { 151 writel(value, base + offset); 152 } 153 154 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap) 155 { 156 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS + 157 omap->utmi_otg_offset); 158 } 159 160 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value) 161 { 162 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS + 163 omap->utmi_otg_offset, value); 164 165 } 166 167 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) 168 { 169 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 - 170 omap->irq0_offset); 171 } 172 173 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) 174 { 175 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - 176 omap->irq0_offset, value); 177 178 } 179 180 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) 181 { 182 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC + 183 omap->irqmisc_offset); 184 } 185 186 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) 187 { 188 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + 189 omap->irqmisc_offset, value); 190 191 } 192 193 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) 194 { 195 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + 196 omap->irqmisc_offset, value); 197 198 } 199 200 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) 201 { 202 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - 203 omap->irq0_offset, value); 204 } 205 206 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, 207 enum omap_dwc3_vbus_id_status status) 208 { 209 int ret; 210 u32 val; 211 212 switch (status) { 213 case OMAP_DWC3_ID_GROUND: 214 dev_dbg(omap->dev, "ID GND\n"); 215 216 if (omap->vbus_reg) { 217 ret = regulator_enable(omap->vbus_reg); 218 if (ret) { 219 dev_dbg(omap->dev, "regulator enable failed\n"); 220 return; 221 } 222 } 223 224 val = dwc3_omap_read_utmi_status(omap); 225 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG 226 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 227 | USBOTGSS_UTMI_OTG_STATUS_SESSEND); 228 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID 229 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; 230 dwc3_omap_write_utmi_status(omap, val); 231 break; 232 233 case OMAP_DWC3_VBUS_VALID: 234 dev_dbg(omap->dev, "VBUS Connect\n"); 235 236 val = dwc3_omap_read_utmi_status(omap); 237 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND; 238 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG 239 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 240 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID 241 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; 242 dwc3_omap_write_utmi_status(omap, val); 243 break; 244 245 case OMAP_DWC3_ID_FLOAT: 246 if (omap->vbus_reg) 247 regulator_disable(omap->vbus_reg); 248 249 case OMAP_DWC3_VBUS_OFF: 250 dev_dbg(omap->dev, "VBUS Disconnect\n"); 251 252 val = dwc3_omap_read_utmi_status(omap); 253 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID 254 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 255 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT); 256 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND 257 | USBOTGSS_UTMI_OTG_STATUS_IDDIG; 258 dwc3_omap_write_utmi_status(omap, val); 259 break; 260 261 default: 262 dev_dbg(omap->dev, "invalid state\n"); 263 } 264 } 265 266 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 267 { 268 struct dwc3_omap *omap = _omap; 269 u32 reg; 270 271 reg = dwc3_omap_read_irqmisc_status(omap); 272 273 if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) { 274 dev_dbg(omap->dev, "DMA Disable was Cleared\n"); 275 omap->dma_status = false; 276 } 277 278 if (reg & USBOTGSS_IRQMISC_OEVT) 279 dev_dbg(omap->dev, "OTG Event\n"); 280 281 if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE) 282 dev_dbg(omap->dev, "DRVVBUS Rise\n"); 283 284 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE) 285 dev_dbg(omap->dev, "CHRGVBUS Rise\n"); 286 287 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE) 288 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n"); 289 290 if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE) 291 dev_dbg(omap->dev, "IDPULLUP Rise\n"); 292 293 if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL) 294 dev_dbg(omap->dev, "DRVVBUS Fall\n"); 295 296 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL) 297 dev_dbg(omap->dev, "CHRGVBUS Fall\n"); 298 299 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL) 300 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n"); 301 302 if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL) 303 dev_dbg(omap->dev, "IDPULLUP Fall\n"); 304 305 dwc3_omap_write_irqmisc_status(omap, reg); 306 307 reg = dwc3_omap_read_irq0_status(omap); 308 309 dwc3_omap_write_irq0_status(omap, reg); 310 311 return IRQ_HANDLED; 312 } 313 314 static int dwc3_omap_remove_core(struct device *dev, void *c) 315 { 316 struct platform_device *pdev = to_platform_device(dev); 317 318 of_device_unregister(pdev); 319 320 return 0; 321 } 322 323 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) 324 { 325 u32 reg; 326 327 /* enable all IRQs */ 328 reg = USBOTGSS_IRQO_COREIRQ_ST; 329 dwc3_omap_write_irq0_set(omap, reg); 330 331 reg = (USBOTGSS_IRQMISC_OEVT | 332 USBOTGSS_IRQMISC_DRVVBUS_RISE | 333 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 334 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 335 USBOTGSS_IRQMISC_IDPULLUP_RISE | 336 USBOTGSS_IRQMISC_DRVVBUS_FALL | 337 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 338 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 339 USBOTGSS_IRQMISC_IDPULLUP_FALL); 340 341 dwc3_omap_write_irqmisc_set(omap, reg); 342 } 343 344 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) 345 { 346 /* disable all IRQs */ 347 dwc3_omap_write_irqmisc_set(omap, 0x00); 348 dwc3_omap_write_irq0_set(omap, 0x00); 349 } 350 351 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32); 352 353 static int dwc3_omap_id_notifier(struct notifier_block *nb, 354 unsigned long event, void *ptr) 355 { 356 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb); 357 358 if (event) 359 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 360 else 361 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT); 362 363 return NOTIFY_DONE; 364 } 365 366 static int dwc3_omap_vbus_notifier(struct notifier_block *nb, 367 unsigned long event, void *ptr) 368 { 369 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb); 370 371 if (event) 372 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 373 else 374 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF); 375 376 return NOTIFY_DONE; 377 } 378 379 static void dwc3_omap_map_offset(struct dwc3_omap *omap) 380 { 381 struct device_node *node = omap->dev->of_node; 382 383 /* 384 * Differentiate between OMAP5 and AM437x. 385 * 386 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even 387 * though there are changes in wrapper register offsets. 388 * 389 * Using dt compatible to differentiate AM437x. 390 */ 391 if (of_device_is_compatible(node, "ti,am437x-dwc3")) { 392 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET; 393 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET; 394 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET; 395 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET; 396 omap->debug_offset = USBOTGSS_DEBUG_OFFSET; 397 } 398 } 399 400 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap) 401 { 402 u32 reg; 403 struct device_node *node = omap->dev->of_node; 404 int utmi_mode = 0; 405 406 reg = dwc3_omap_read_utmi_status(omap); 407 408 of_property_read_u32(node, "utmi-mode", &utmi_mode); 409 410 switch (utmi_mode) { 411 case DWC3_OMAP_UTMI_MODE_SW: 412 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 413 break; 414 case DWC3_OMAP_UTMI_MODE_HW: 415 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 416 break; 417 default: 418 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode); 419 } 420 421 dwc3_omap_write_utmi_status(omap, reg); 422 } 423 424 static int dwc3_omap_extcon_register(struct dwc3_omap *omap) 425 { 426 int ret; 427 struct device_node *node = omap->dev->of_node; 428 struct extcon_dev *edev; 429 430 if (of_property_read_bool(node, "extcon")) { 431 edev = extcon_get_edev_by_phandle(omap->dev, 0); 432 if (IS_ERR(edev)) { 433 dev_vdbg(omap->dev, "couldn't get extcon device\n"); 434 return -EPROBE_DEFER; 435 } 436 437 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier; 438 ret = extcon_register_interest(&omap->extcon_vbus_dev, 439 edev->name, "USB", 440 &omap->vbus_nb); 441 if (ret < 0) 442 dev_vdbg(omap->dev, "failed to register notifier for USB\n"); 443 444 omap->id_nb.notifier_call = dwc3_omap_id_notifier; 445 ret = extcon_register_interest(&omap->extcon_id_dev, 446 edev->name, "USB-HOST", 447 &omap->id_nb); 448 if (ret < 0) 449 dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n"); 450 451 if (extcon_get_cable_state(edev, "USB") == true) 452 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 453 if (extcon_get_cable_state(edev, "USB-HOST") == true) 454 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 455 } 456 457 return 0; 458 } 459 460 static int dwc3_omap_probe(struct platform_device *pdev) 461 { 462 struct device_node *node = pdev->dev.of_node; 463 464 struct dwc3_omap *omap; 465 struct resource *res; 466 struct device *dev = &pdev->dev; 467 struct regulator *vbus_reg = NULL; 468 469 int ret; 470 int irq; 471 472 u32 reg; 473 474 void __iomem *base; 475 476 if (!node) { 477 dev_err(dev, "device node not found\n"); 478 return -EINVAL; 479 } 480 481 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); 482 if (!omap) 483 return -ENOMEM; 484 485 platform_set_drvdata(pdev, omap); 486 487 irq = platform_get_irq(pdev, 0); 488 if (irq < 0) { 489 dev_err(dev, "missing IRQ resource\n"); 490 return -EINVAL; 491 } 492 493 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 494 base = devm_ioremap_resource(dev, res); 495 if (IS_ERR(base)) 496 return PTR_ERR(base); 497 498 if (of_property_read_bool(node, "vbus-supply")) { 499 vbus_reg = devm_regulator_get(dev, "vbus"); 500 if (IS_ERR(vbus_reg)) { 501 dev_err(dev, "vbus init failed\n"); 502 return PTR_ERR(vbus_reg); 503 } 504 } 505 506 omap->dev = dev; 507 omap->irq = irq; 508 omap->base = base; 509 omap->vbus_reg = vbus_reg; 510 dev->dma_mask = &dwc3_omap_dma_mask; 511 512 pm_runtime_enable(dev); 513 ret = pm_runtime_get_sync(dev); 514 if (ret < 0) { 515 dev_err(dev, "get_sync failed with err %d\n", ret); 516 goto err0; 517 } 518 519 dwc3_omap_map_offset(omap); 520 dwc3_omap_set_utmi_mode(omap); 521 522 /* check the DMA Status */ 523 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); 524 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE); 525 526 ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0, 527 "dwc3-omap", omap); 528 if (ret) { 529 dev_err(dev, "failed to request IRQ #%d --> %d\n", 530 omap->irq, ret); 531 goto err1; 532 } 533 534 dwc3_omap_enable_irqs(omap); 535 536 ret = dwc3_omap_extcon_register(omap); 537 if (ret < 0) 538 goto err2; 539 540 ret = of_platform_populate(node, NULL, NULL, dev); 541 if (ret) { 542 dev_err(&pdev->dev, "failed to create dwc3 core\n"); 543 goto err3; 544 } 545 546 return 0; 547 548 err3: 549 if (omap->extcon_vbus_dev.edev) 550 extcon_unregister_interest(&omap->extcon_vbus_dev); 551 if (omap->extcon_id_dev.edev) 552 extcon_unregister_interest(&omap->extcon_id_dev); 553 554 err2: 555 dwc3_omap_disable_irqs(omap); 556 557 err1: 558 pm_runtime_put_sync(dev); 559 560 err0: 561 pm_runtime_disable(dev); 562 563 return ret; 564 } 565 566 static int dwc3_omap_remove(struct platform_device *pdev) 567 { 568 struct dwc3_omap *omap = platform_get_drvdata(pdev); 569 570 if (omap->extcon_vbus_dev.edev) 571 extcon_unregister_interest(&omap->extcon_vbus_dev); 572 if (omap->extcon_id_dev.edev) 573 extcon_unregister_interest(&omap->extcon_id_dev); 574 dwc3_omap_disable_irqs(omap); 575 device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core); 576 pm_runtime_put_sync(&pdev->dev); 577 pm_runtime_disable(&pdev->dev); 578 579 return 0; 580 } 581 582 static const struct of_device_id of_dwc3_match[] = { 583 { 584 .compatible = "ti,dwc3" 585 }, 586 { 587 .compatible = "ti,am437x-dwc3" 588 }, 589 { }, 590 }; 591 MODULE_DEVICE_TABLE(of, of_dwc3_match); 592 593 #ifdef CONFIG_PM_SLEEP 594 static int dwc3_omap_suspend(struct device *dev) 595 { 596 struct dwc3_omap *omap = dev_get_drvdata(dev); 597 598 omap->utmi_otg_status = dwc3_omap_read_utmi_status(omap); 599 dwc3_omap_disable_irqs(omap); 600 601 return 0; 602 } 603 604 static int dwc3_omap_resume(struct device *dev) 605 { 606 struct dwc3_omap *omap = dev_get_drvdata(dev); 607 608 dwc3_omap_write_utmi_status(omap, omap->utmi_otg_status); 609 dwc3_omap_enable_irqs(omap); 610 611 pm_runtime_disable(dev); 612 pm_runtime_set_active(dev); 613 pm_runtime_enable(dev); 614 615 return 0; 616 } 617 618 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = { 619 620 SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume) 621 }; 622 623 #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops) 624 #else 625 #define DEV_PM_OPS NULL 626 #endif /* CONFIG_PM_SLEEP */ 627 628 static struct platform_driver dwc3_omap_driver = { 629 .probe = dwc3_omap_probe, 630 .remove = dwc3_omap_remove, 631 .driver = { 632 .name = "omap-dwc3", 633 .of_match_table = of_dwc3_match, 634 .pm = DEV_PM_OPS, 635 }, 636 }; 637 638 module_platform_driver(dwc3_omap_driver); 639 640 MODULE_ALIAS("platform:omap-dwc3"); 641 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 642 MODULE_LICENSE("GPL v2"); 643 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); 644