1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /** 3 * core.h - DesignWare USB3 DRD Core Header 4 * 5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 * 10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.h) and ported 11 * to uboot. 12 * 13 * commit 460d098cb6 : usb: dwc3: make HIRD threshold configurable 14 * 15 */ 16 17 #ifndef __DRIVERS_USB_DWC3_CORE_H 18 #define __DRIVERS_USB_DWC3_CORE_H 19 20 #include <linux/ioport.h> 21 22 #include <linux/usb/ch9.h> 23 #include <linux/usb/otg.h> 24 25 #define DWC3_MSG_MAX 500 26 27 /* Global constants */ 28 #define DWC3_EP0_BOUNCE_SIZE 512 29 #define DWC3_ENDPOINTS_NUM 32 30 #define DWC3_XHCI_RESOURCES_NUM 2 31 32 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 33 #define DWC3_EVENT_SIZE 4 /* bytes */ 34 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 35 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 36 #define DWC3_EVENT_TYPE_MASK 0xfe 37 38 #define DWC3_EVENT_TYPE_DEV 0 39 #define DWC3_EVENT_TYPE_CARKIT 3 40 #define DWC3_EVENT_TYPE_I2C 4 41 42 #define DWC3_DEVICE_EVENT_DISCONNECT 0 43 #define DWC3_DEVICE_EVENT_RESET 1 44 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 45 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 46 #define DWC3_DEVICE_EVENT_WAKEUP 4 47 #define DWC3_DEVICE_EVENT_HIBER_REQ 5 48 #define DWC3_DEVICE_EVENT_EOPF 6 49 #define DWC3_DEVICE_EVENT_SOF 7 50 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 51 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 52 #define DWC3_DEVICE_EVENT_OVERFLOW 11 53 54 #define DWC3_GEVNTCOUNT_MASK 0xfffc 55 #define DWC3_GSNPSID_MASK 0xffff0000 56 #define DWC3_GSNPSREV_MASK 0xffff 57 58 /* DWC3 registers memory space boundries */ 59 #define DWC3_XHCI_REGS_START 0x0 60 #define DWC3_XHCI_REGS_END 0x7fff 61 #define DWC3_GLOBALS_REGS_START 0xc100 62 #define DWC3_GLOBALS_REGS_END 0xc6ff 63 #define DWC3_DEVICE_REGS_START 0xc700 64 #define DWC3_DEVICE_REGS_END 0xcbff 65 #define DWC3_OTG_REGS_START 0xcc00 66 #define DWC3_OTG_REGS_END 0xccff 67 68 /* Global Registers */ 69 #define DWC3_GSBUSCFG0 0xc100 70 #define DWC3_GSBUSCFG1 0xc104 71 #define DWC3_GTXTHRCFG 0xc108 72 #define DWC3_GRXTHRCFG 0xc10c 73 #define DWC3_GCTL 0xc110 74 #define DWC3_GEVTEN 0xc114 75 #define DWC3_GSTS 0xc118 76 #define DWC3_GSNPSID 0xc120 77 #define DWC3_GGPIO 0xc124 78 #define DWC3_GUID 0xc128 79 #define DWC3_GUCTL 0xc12c 80 #define DWC3_GBUSERRADDR0 0xc130 81 #define DWC3_GBUSERRADDR1 0xc134 82 #define DWC3_GPRTBIMAP0 0xc138 83 #define DWC3_GPRTBIMAP1 0xc13c 84 #define DWC3_GHWPARAMS0 0xc140 85 #define DWC3_GHWPARAMS1 0xc144 86 #define DWC3_GHWPARAMS2 0xc148 87 #define DWC3_GHWPARAMS3 0xc14c 88 #define DWC3_GHWPARAMS4 0xc150 89 #define DWC3_GHWPARAMS5 0xc154 90 #define DWC3_GHWPARAMS6 0xc158 91 #define DWC3_GHWPARAMS7 0xc15c 92 #define DWC3_GDBGFIFOSPACE 0xc160 93 #define DWC3_GDBGLTSSM 0xc164 94 #define DWC3_GPRTBIMAP_HS0 0xc180 95 #define DWC3_GPRTBIMAP_HS1 0xc184 96 #define DWC3_GPRTBIMAP_FS0 0xc188 97 #define DWC3_GPRTBIMAP_FS1 0xc18c 98 99 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 100 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 101 102 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 103 104 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 105 106 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 107 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 108 109 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 110 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 111 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 112 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 113 114 #define DWC3_GHWPARAMS8 0xc600 115 116 /* Device Registers */ 117 #define DWC3_DCFG 0xc700 118 #define DWC3_DCTL 0xc704 119 #define DWC3_DEVTEN 0xc708 120 #define DWC3_DSTS 0xc70c 121 #define DWC3_DGCMDPAR 0xc710 122 #define DWC3_DGCMD 0xc714 123 #define DWC3_DALEPENA 0xc720 124 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 125 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 126 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 127 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 128 129 /* OTG Registers */ 130 #define DWC3_OCFG 0xcc00 131 #define DWC3_OCTL 0xcc04 132 #define DWC3_OEVT 0xcc08 133 #define DWC3_OEVTEN 0xcc0C 134 #define DWC3_OSTS 0xcc10 135 136 /* Bit fields */ 137 138 /* Global Configuration Register */ 139 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 140 #define DWC3_GCTL_U2RSTECN (1 << 16) 141 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 142 #define DWC3_GCTL_CLK_BUS (0) 143 #define DWC3_GCTL_CLK_PIPE (1) 144 #define DWC3_GCTL_CLK_PIPEHALF (2) 145 #define DWC3_GCTL_CLK_MASK (3) 146 147 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 148 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 149 #define DWC3_GCTL_PRTCAP_HOST 1 150 #define DWC3_GCTL_PRTCAP_DEVICE 2 151 #define DWC3_GCTL_PRTCAP_OTG 3 152 153 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 154 #define DWC3_GCTL_SOFITPSYNC (1 << 10) 155 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 156 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 157 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 158 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) 159 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 160 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 161 162 /* Global USB2 PHY Configuration Register */ 163 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 164 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 165 166 /* Global USB3 PIPE Control Register */ 167 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 168 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) 169 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) 170 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 171 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 172 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 173 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) 174 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 175 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) 176 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) 177 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 178 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 179 180 /* Global TX Fifo Size Register */ 181 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 182 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 183 184 /* Global Event Size Registers */ 185 #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 186 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 187 188 /* Global HWPARAMS1 Register */ 189 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 190 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 191 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 192 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 193 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 194 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 195 196 /* Global HWPARAMS3 Register */ 197 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 198 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 199 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 200 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 201 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 202 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 203 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 204 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 205 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 206 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 207 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 208 209 /* Global HWPARAMS4 Register */ 210 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 211 #define DWC3_MAX_HIBER_SCRATCHBUFS 15 212 213 /* Global HWPARAMS6 Register */ 214 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) 215 216 /* Device Configuration Register */ 217 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 218 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 219 220 #define DWC3_DCFG_SPEED_MASK (7 << 0) 221 #define DWC3_DCFG_SUPERSPEED (4 << 0) 222 #define DWC3_DCFG_HIGHSPEED (0 << 0) 223 #define DWC3_DCFG_FULLSPEED2 (1 << 0) 224 #define DWC3_DCFG_LOWSPEED (2 << 0) 225 #define DWC3_DCFG_FULLSPEED1 (3 << 0) 226 227 #define DWC3_DCFG_LPM_CAP (1 << 22) 228 229 /* Device Control Register */ 230 #define DWC3_DCTL_RUN_STOP (1 << 31) 231 #define DWC3_DCTL_CSFTRST (1 << 30) 232 #define DWC3_DCTL_LSFTRST (1 << 29) 233 234 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 235 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 236 237 #define DWC3_DCTL_APPL1RES (1 << 23) 238 239 /* These apply for core versions 1.87a and earlier */ 240 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 241 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 242 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 243 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 244 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 245 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 246 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 247 248 /* These apply for core versions 1.94a and later */ 249 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 250 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 251 252 #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 253 #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 254 #define DWC3_DCTL_CRS (1 << 17) 255 #define DWC3_DCTL_CSS (1 << 16) 256 257 #define DWC3_DCTL_INITU2ENA (1 << 12) 258 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 259 #define DWC3_DCTL_INITU1ENA (1 << 10) 260 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 261 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 262 263 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 264 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 265 266 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 267 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 268 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 269 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 270 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 271 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 272 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 273 274 /* Device Event Enable Register */ 275 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 276 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 277 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 278 #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 279 #define DWC3_DEVTEN_SOFEN (1 << 7) 280 #define DWC3_DEVTEN_EOPFEN (1 << 6) 281 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 282 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 283 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 284 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 285 #define DWC3_DEVTEN_USBRSTEN (1 << 1) 286 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 287 288 /* Device Status Register */ 289 #define DWC3_DSTS_DCNRD (1 << 29) 290 291 /* This applies for core versions 1.87a and earlier */ 292 #define DWC3_DSTS_PWRUPREQ (1 << 24) 293 294 /* These apply for core versions 1.94a and later */ 295 #define DWC3_DSTS_RSS (1 << 25) 296 #define DWC3_DSTS_SSS (1 << 24) 297 298 #define DWC3_DSTS_COREIDLE (1 << 23) 299 #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 300 301 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 302 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 303 304 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 305 306 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 307 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 308 309 #define DWC3_DSTS_CONNECTSPD (7 << 0) 310 311 #define DWC3_DSTS_SUPERSPEED (4 << 0) 312 #define DWC3_DSTS_HIGHSPEED (0 << 0) 313 #define DWC3_DSTS_FULLSPEED2 (1 << 0) 314 #define DWC3_DSTS_LOWSPEED (2 << 0) 315 #define DWC3_DSTS_FULLSPEED1 (3 << 0) 316 317 /* Device Generic Command Register */ 318 #define DWC3_DGCMD_SET_LMP 0x01 319 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 320 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 321 322 /* These apply for core versions 1.94a and later */ 323 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 324 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 325 326 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 327 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 328 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 329 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 330 331 #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 332 #define DWC3_DGCMD_CMDACT (1 << 10) 333 #define DWC3_DGCMD_CMDIOC (1 << 8) 334 335 /* Device Generic Command Parameter Register */ 336 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 337 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 338 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 339 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 340 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 341 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 342 343 /* Device Endpoint Command Register */ 344 #define DWC3_DEPCMD_PARAM_SHIFT 16 345 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 346 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 347 #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 348 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 349 #define DWC3_DEPCMD_CMDACT (1 << 10) 350 #define DWC3_DEPCMD_CMDIOC (1 << 8) 351 352 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 353 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 354 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 355 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 356 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 357 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 358 /* This applies for core versions 1.90a and earlier */ 359 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 360 /* This applies for core versions 1.94a and later */ 361 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 362 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 363 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 364 365 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 366 #define DWC3_DALEPENA_EP(n) (1 << n) 367 368 #define DWC3_DEPCMD_TYPE_CONTROL 0 369 #define DWC3_DEPCMD_TYPE_ISOC 1 370 #define DWC3_DEPCMD_TYPE_BULK 2 371 #define DWC3_DEPCMD_TYPE_INTR 3 372 373 /* Structures */ 374 375 struct dwc3_trb; 376 377 /** 378 * struct dwc3_event_buffer - Software event buffer representation 379 * @buf: _THE_ buffer 380 * @length: size of this buffer 381 * @lpos: event offset 382 * @count: cache of last read event count register 383 * @flags: flags related to this event buffer 384 * @dma: dma_addr_t 385 * @dwc: pointer to DWC controller 386 */ 387 struct dwc3_event_buffer { 388 void *buf; 389 unsigned length; 390 unsigned int lpos; 391 unsigned int count; 392 unsigned int flags; 393 394 #define DWC3_EVENT_PENDING (1UL << 0) 395 396 dma_addr_t dma; 397 398 struct dwc3 *dwc; 399 }; 400 401 #define DWC3_EP_FLAG_STALLED (1 << 0) 402 #define DWC3_EP_FLAG_WEDGED (1 << 1) 403 404 #define DWC3_EP_DIRECTION_TX true 405 #define DWC3_EP_DIRECTION_RX false 406 407 #define DWC3_TRB_NUM 32 408 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 409 410 /** 411 * struct dwc3_ep - device side endpoint representation 412 * @endpoint: usb endpoint 413 * @request_list: list of requests for this endpoint 414 * @req_queued: list of requests on this ep which have TRBs setup 415 * @trb_pool: array of transaction buffers 416 * @trb_pool_dma: dma address of @trb_pool 417 * @free_slot: next slot which is going to be used 418 * @busy_slot: first slot which is owned by HW 419 * @desc: usb_endpoint_descriptor pointer 420 * @dwc: pointer to DWC controller 421 * @saved_state: ep state saved during hibernation 422 * @flags: endpoint flags (wedged, stalled, ...) 423 * @current_trb: index of current used trb 424 * @number: endpoint number (1 - 15) 425 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 426 * @resource_index: Resource transfer index 427 * @interval: the interval on which the ISOC transfer is started 428 * @name: a human readable name e.g. ep1out-bulk 429 * @direction: true for TX, false for RX 430 * @stream_capable: true when streams are enabled 431 */ 432 struct dwc3_ep { 433 struct usb_ep endpoint; 434 struct list_head request_list; 435 struct list_head req_queued; 436 437 struct dwc3_trb *trb_pool; 438 dma_addr_t trb_pool_dma; 439 u32 free_slot; 440 u32 busy_slot; 441 const struct usb_ss_ep_comp_descriptor *comp_desc; 442 struct dwc3 *dwc; 443 444 u32 saved_state; 445 unsigned flags; 446 #define DWC3_EP_ENABLED (1 << 0) 447 #define DWC3_EP_STALL (1 << 1) 448 #define DWC3_EP_WEDGE (1 << 2) 449 #define DWC3_EP_BUSY (1 << 4) 450 #define DWC3_EP_PENDING_REQUEST (1 << 5) 451 #define DWC3_EP_MISSED_ISOC (1 << 6) 452 453 /* This last one is specific to EP0 */ 454 #define DWC3_EP0_DIR_IN (1 << 31) 455 456 unsigned current_trb; 457 458 u8 number; 459 u8 type; 460 u8 resource_index; 461 u32 interval; 462 463 char name[20]; 464 465 unsigned direction:1; 466 unsigned stream_capable:1; 467 }; 468 469 enum dwc3_phy { 470 DWC3_PHY_UNKNOWN = 0, 471 DWC3_PHY_USB3, 472 DWC3_PHY_USB2, 473 }; 474 475 enum dwc3_ep0_next { 476 DWC3_EP0_UNKNOWN = 0, 477 DWC3_EP0_COMPLETE, 478 DWC3_EP0_NRDY_DATA, 479 DWC3_EP0_NRDY_STATUS, 480 }; 481 482 enum dwc3_ep0_state { 483 EP0_UNCONNECTED = 0, 484 EP0_SETUP_PHASE, 485 EP0_DATA_PHASE, 486 EP0_STATUS_PHASE, 487 }; 488 489 enum dwc3_link_state { 490 /* In SuperSpeed */ 491 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 492 DWC3_LINK_STATE_U1 = 0x01, 493 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 494 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 495 DWC3_LINK_STATE_SS_DIS = 0x04, 496 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 497 DWC3_LINK_STATE_SS_INACT = 0x06, 498 DWC3_LINK_STATE_POLL = 0x07, 499 DWC3_LINK_STATE_RECOV = 0x08, 500 DWC3_LINK_STATE_HRESET = 0x09, 501 DWC3_LINK_STATE_CMPLY = 0x0a, 502 DWC3_LINK_STATE_LPBK = 0x0b, 503 DWC3_LINK_STATE_RESET = 0x0e, 504 DWC3_LINK_STATE_RESUME = 0x0f, 505 DWC3_LINK_STATE_MASK = 0x0f, 506 }; 507 508 /* TRB Length, PCM and Status */ 509 #define DWC3_TRB_SIZE_MASK (0x00ffffff) 510 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 511 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 512 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 513 514 #define DWC3_TRBSTS_OK 0 515 #define DWC3_TRBSTS_MISSED_ISOC 1 516 #define DWC3_TRBSTS_SETUP_PENDING 2 517 #define DWC3_TRB_STS_XFER_IN_PROG 4 518 519 /* TRB Control */ 520 #define DWC3_TRB_CTRL_HWO (1 << 0) 521 #define DWC3_TRB_CTRL_LST (1 << 1) 522 #define DWC3_TRB_CTRL_CHN (1 << 2) 523 #define DWC3_TRB_CTRL_CSP (1 << 3) 524 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 525 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 526 #define DWC3_TRB_CTRL_IOC (1 << 11) 527 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 528 529 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 530 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 531 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 532 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 533 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 534 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 535 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 536 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 537 538 /** 539 * struct dwc3_trb - transfer request block (hw format) 540 * @bpl: DW0-3 541 * @bph: DW4-7 542 * @size: DW8-B 543 * @trl: DWC-F 544 */ 545 struct dwc3_trb { 546 u32 bpl; 547 u32 bph; 548 u32 size; 549 u32 ctrl; 550 } __packed; 551 552 /** 553 * dwc3_hwparams - copy of HWPARAMS registers 554 * @hwparams0 - GHWPARAMS0 555 * @hwparams1 - GHWPARAMS1 556 * @hwparams2 - GHWPARAMS2 557 * @hwparams3 - GHWPARAMS3 558 * @hwparams4 - GHWPARAMS4 559 * @hwparams5 - GHWPARAMS5 560 * @hwparams6 - GHWPARAMS6 561 * @hwparams7 - GHWPARAMS7 562 * @hwparams8 - GHWPARAMS8 563 */ 564 struct dwc3_hwparams { 565 u32 hwparams0; 566 u32 hwparams1; 567 u32 hwparams2; 568 u32 hwparams3; 569 u32 hwparams4; 570 u32 hwparams5; 571 u32 hwparams6; 572 u32 hwparams7; 573 u32 hwparams8; 574 }; 575 576 /* HWPARAMS0 */ 577 #define DWC3_MODE(n) ((n) & 0x7) 578 579 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 580 581 /* HWPARAMS1 */ 582 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 583 584 /* HWPARAMS3 */ 585 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 586 #define DWC3_NUM_EPS_MASK (0x3f << 12) 587 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 588 (DWC3_NUM_EPS_MASK)) >> 12) 589 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 590 (DWC3_NUM_IN_EPS_MASK)) >> 18) 591 592 /* HWPARAMS7 */ 593 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 594 595 struct dwc3_request { 596 struct usb_request request; 597 struct list_head list; 598 struct dwc3_ep *dep; 599 u32 start_slot; 600 601 u8 epnum; 602 struct dwc3_trb *trb; 603 dma_addr_t trb_dma; 604 605 unsigned direction:1; 606 unsigned mapped:1; 607 unsigned queued:1; 608 }; 609 610 /* 611 * struct dwc3_scratchpad_array - hibernation scratchpad array 612 * (format defined by hw) 613 */ 614 struct dwc3_scratchpad_array { 615 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 616 }; 617 618 /** 619 * struct dwc3 - representation of our controller 620 * @ctrl_req: usb control request which is used for ep0 621 * @ep0_trb: trb which is used for the ctrl_req 622 * @ep0_bounce: bounce buffer for ep0 623 * @setup_buf: used while precessing STD USB requests 624 * @ctrl_req_addr: dma address of ctrl_req 625 * @ep0_trb: dma address of ep0_trb 626 * @ep0_usb_req: dummy req used while handling STD USB requests 627 * @ep0_bounce_addr: dma address of ep0_bounce 628 * @scratch_addr: dma address of scratchbuf 629 * @lock: for synchronizing 630 * @dev: pointer to our struct device 631 * @xhci: pointer to our xHCI child 632 * @event_buffer_list: a list of event buffers 633 * @gadget: device side representation of the peripheral controller 634 * @gadget_driver: pointer to the gadget driver 635 * @regs: base address for our registers 636 * @regs_size: address space size 637 * @nr_scratch: number of scratch buffers 638 * @num_event_buffers: calculated number of event buffers 639 * @u1u2: only used on revisions <1.83a for workaround 640 * @maximum_speed: maximum speed requested (mainly for testing purposes) 641 * @revision: revision register contents 642 * @dr_mode: requested mode of operation 643 * @dcfg: saved contents of DCFG register 644 * @gctl: saved contents of GCTL register 645 * @isoch_delay: wValue from Set Isochronous Delay request; 646 * @u2sel: parameter from Set SEL request. 647 * @u2pel: parameter from Set SEL request. 648 * @u1sel: parameter from Set SEL request. 649 * @u1pel: parameter from Set SEL request. 650 * @num_out_eps: number of out endpoints 651 * @num_in_eps: number of in endpoints 652 * @ep0_next_event: hold the next expected event 653 * @ep0state: state of endpoint zero 654 * @link_state: link state 655 * @speed: device speed (super, high, full, low) 656 * @mem: points to start of memory which is used for this struct. 657 * @hwparams: copy of hwparams registers 658 * @root: debugfs root folder pointer 659 * @regset: debugfs pointer to regdump file 660 * @test_mode: true when we're entering a USB test mode 661 * @test_mode_nr: test feature selector 662 * @lpm_nyet_threshold: LPM NYET response threshold 663 * @hird_threshold: HIRD threshold 664 * @delayed_status: true when gadget driver asks for delayed status 665 * @ep0_bounced: true when we used bounce buffer 666 * @ep0_expect_in: true when we expect a DATA IN transfer 667 * @has_hibernation: true when dwc3 was configured with Hibernation 668 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 669 * there's now way for software to detect this in runtime. 670 * @is_utmi_l1_suspend: the core asserts output signal 671 * 0 - utmi_sleep_n 672 * 1 - utmi_l1_suspend_n 673 * @is_selfpowered: true when we are selfpowered 674 * @is_fpga: true when we are using the FPGA board 675 * @needs_fifo_resize: not all users might want fifo resizing, flag it 676 * @pullups_connected: true when Run/Stop bit is set 677 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 678 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 679 * @start_config_issued: true when StartConfig command has been issued 680 * @three_stage_setup: set if we perform a three phase setup 681 * @disable_scramble_quirk: set if we enable the disable scramble quirk 682 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 683 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 684 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 685 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 686 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 687 * @lfps_filter_quirk: set if we enable LFPS filter quirk 688 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 689 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 690 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 691 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 692 * @tx_de_emphasis: Tx de-emphasis value 693 * 0 - -6dB de-emphasis 694 * 1 - -3.5dB de-emphasis 695 * 2 - No de-emphasis 696 * 3 - Reserved 697 * @index: index of _this_ controller 698 * @list: to maintain the list of dwc3 controllers 699 */ 700 struct dwc3 { 701 struct usb_ctrlrequest *ctrl_req; 702 struct dwc3_trb *ep0_trb; 703 void *ep0_bounce; 704 void *scratchbuf; 705 u8 *setup_buf; 706 dma_addr_t ctrl_req_addr; 707 dma_addr_t ep0_trb_addr; 708 dma_addr_t ep0_bounce_addr; 709 dma_addr_t scratch_addr; 710 struct dwc3_request ep0_usb_req; 711 712 /* device lock */ 713 spinlock_t lock; 714 715 #if defined(__UBOOT__) && CONFIG_IS_ENABLED(DM_USB) 716 struct udevice *dev; 717 #else 718 struct device *dev; 719 #endif 720 721 struct platform_device *xhci; 722 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 723 724 struct dwc3_event_buffer **ev_buffs; 725 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 726 727 struct usb_gadget gadget; 728 struct usb_gadget_driver *gadget_driver; 729 730 void __iomem *regs; 731 size_t regs_size; 732 733 enum usb_dr_mode dr_mode; 734 735 /* used for suspend/resume */ 736 u32 dcfg; 737 u32 gctl; 738 739 u32 nr_scratch; 740 u32 num_event_buffers; 741 u32 u1u2; 742 u32 maximum_speed; 743 u32 revision; 744 745 #define DWC3_REVISION_173A 0x5533173a 746 #define DWC3_REVISION_175A 0x5533175a 747 #define DWC3_REVISION_180A 0x5533180a 748 #define DWC3_REVISION_183A 0x5533183a 749 #define DWC3_REVISION_185A 0x5533185a 750 #define DWC3_REVISION_187A 0x5533187a 751 #define DWC3_REVISION_188A 0x5533188a 752 #define DWC3_REVISION_190A 0x5533190a 753 #define DWC3_REVISION_194A 0x5533194a 754 #define DWC3_REVISION_200A 0x5533200a 755 #define DWC3_REVISION_202A 0x5533202a 756 #define DWC3_REVISION_210A 0x5533210a 757 #define DWC3_REVISION_220A 0x5533220a 758 #define DWC3_REVISION_230A 0x5533230a 759 #define DWC3_REVISION_240A 0x5533240a 760 #define DWC3_REVISION_250A 0x5533250a 761 #define DWC3_REVISION_260A 0x5533260a 762 #define DWC3_REVISION_270A 0x5533270a 763 #define DWC3_REVISION_280A 0x5533280a 764 765 enum dwc3_ep0_next ep0_next_event; 766 enum dwc3_ep0_state ep0state; 767 enum dwc3_link_state link_state; 768 769 u16 isoch_delay; 770 u16 u2sel; 771 u16 u2pel; 772 u8 u1sel; 773 u8 u1pel; 774 775 u8 speed; 776 777 u8 num_out_eps; 778 u8 num_in_eps; 779 780 void *mem; 781 782 struct dwc3_hwparams hwparams; 783 struct dentry *root; 784 struct debugfs_regset32 *regset; 785 786 u8 test_mode; 787 u8 test_mode_nr; 788 u8 lpm_nyet_threshold; 789 u8 hird_threshold; 790 791 unsigned delayed_status:1; 792 unsigned ep0_bounced:1; 793 unsigned ep0_expect_in:1; 794 unsigned has_hibernation:1; 795 unsigned has_lpm_erratum:1; 796 unsigned is_utmi_l1_suspend:1; 797 unsigned is_selfpowered:1; 798 unsigned is_fpga:1; 799 unsigned needs_fifo_resize:1; 800 unsigned pullups_connected:1; 801 unsigned resize_fifos:1; 802 unsigned setup_packet_pending:1; 803 unsigned start_config_issued:1; 804 unsigned three_stage_setup:1; 805 806 unsigned disable_scramble_quirk:1; 807 unsigned u2exit_lfps_quirk:1; 808 unsigned u2ss_inp3_quirk:1; 809 unsigned req_p1p2p3_quirk:1; 810 unsigned del_p1p2p3_quirk:1; 811 unsigned del_phy_power_chg_quirk:1; 812 unsigned lfps_filter_quirk:1; 813 unsigned rx_detect_poll_quirk:1; 814 unsigned dis_u3_susphy_quirk:1; 815 unsigned dis_u2_susphy_quirk:1; 816 817 unsigned tx_de_emphasis_quirk:1; 818 unsigned tx_de_emphasis:2; 819 int index; 820 struct list_head list; 821 }; 822 823 /* -------------------------------------------------------------------------- */ 824 825 /* -------------------------------------------------------------------------- */ 826 827 struct dwc3_event_type { 828 u32 is_devspec:1; 829 u32 type:7; 830 u32 reserved8_31:24; 831 } __packed; 832 833 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 834 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 835 #define DWC3_DEPEVT_XFERNOTREADY 0x03 836 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 837 #define DWC3_DEPEVT_STREAMEVT 0x06 838 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 839 840 /** 841 * dwc3_ep_event_string - returns event name 842 * @event: then event code 843 */ 844 static inline const char *dwc3_ep_event_string(u8 event) 845 { 846 switch (event) { 847 case DWC3_DEPEVT_XFERCOMPLETE: 848 return "Transfer Complete"; 849 case DWC3_DEPEVT_XFERINPROGRESS: 850 return "Transfer In-Progress"; 851 case DWC3_DEPEVT_XFERNOTREADY: 852 return "Transfer Not Ready"; 853 case DWC3_DEPEVT_RXTXFIFOEVT: 854 return "FIFO"; 855 case DWC3_DEPEVT_STREAMEVT: 856 return "Stream"; 857 case DWC3_DEPEVT_EPCMDCMPLT: 858 return "Endpoint Command Complete"; 859 } 860 861 return "UNKNOWN"; 862 } 863 864 /** 865 * struct dwc3_event_depvt - Device Endpoint Events 866 * @one_bit: indicates this is an endpoint event (not used) 867 * @endpoint_number: number of the endpoint 868 * @endpoint_event: The event we have: 869 * 0x00 - Reserved 870 * 0x01 - XferComplete 871 * 0x02 - XferInProgress 872 * 0x03 - XferNotReady 873 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 874 * 0x05 - Reserved 875 * 0x06 - StreamEvt 876 * 0x07 - EPCmdCmplt 877 * @reserved11_10: Reserved, don't use. 878 * @status: Indicates the status of the event. Refer to databook for 879 * more information. 880 * @parameters: Parameters of the current event. Refer to databook for 881 * more information. 882 */ 883 struct dwc3_event_depevt { 884 u32 one_bit:1; 885 u32 endpoint_number:5; 886 u32 endpoint_event:4; 887 u32 reserved11_10:2; 888 u32 status:4; 889 890 /* Within XferNotReady */ 891 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 892 893 /* Within XferComplete */ 894 #define DEPEVT_STATUS_BUSERR (1 << 0) 895 #define DEPEVT_STATUS_SHORT (1 << 1) 896 #define DEPEVT_STATUS_IOC (1 << 2) 897 #define DEPEVT_STATUS_LST (1 << 3) 898 899 /* Stream event only */ 900 #define DEPEVT_STREAMEVT_FOUND 1 901 #define DEPEVT_STREAMEVT_NOTFOUND 2 902 903 /* Control-only Status */ 904 #define DEPEVT_STATUS_CONTROL_DATA 1 905 #define DEPEVT_STATUS_CONTROL_STATUS 2 906 907 u32 parameters:16; 908 } __packed; 909 910 /** 911 * struct dwc3_event_devt - Device Events 912 * @one_bit: indicates this is a non-endpoint event (not used) 913 * @device_event: indicates it's a device event. Should read as 0x00 914 * @type: indicates the type of device event. 915 * 0 - DisconnEvt 916 * 1 - USBRst 917 * 2 - ConnectDone 918 * 3 - ULStChng 919 * 4 - WkUpEvt 920 * 5 - Reserved 921 * 6 - EOPF 922 * 7 - SOF 923 * 8 - Reserved 924 * 9 - ErrticErr 925 * 10 - CmdCmplt 926 * 11 - EvntOverflow 927 * 12 - VndrDevTstRcved 928 * @reserved15_12: Reserved, not used 929 * @event_info: Information about this event 930 * @reserved31_25: Reserved, not used 931 */ 932 struct dwc3_event_devt { 933 u32 one_bit:1; 934 u32 device_event:7; 935 u32 type:4; 936 u32 reserved15_12:4; 937 u32 event_info:9; 938 u32 reserved31_25:7; 939 } __packed; 940 941 /** 942 * struct dwc3_event_gevt - Other Core Events 943 * @one_bit: indicates this is a non-endpoint event (not used) 944 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 945 * @phy_port_number: self-explanatory 946 * @reserved31_12: Reserved, not used. 947 */ 948 struct dwc3_event_gevt { 949 u32 one_bit:1; 950 u32 device_event:7; 951 u32 phy_port_number:4; 952 u32 reserved31_12:20; 953 } __packed; 954 955 /** 956 * union dwc3_event - representation of Event Buffer contents 957 * @raw: raw 32-bit event 958 * @type: the type of the event 959 * @depevt: Device Endpoint Event 960 * @devt: Device Event 961 * @gevt: Global Event 962 */ 963 union dwc3_event { 964 u32 raw; 965 struct dwc3_event_type type; 966 struct dwc3_event_depevt depevt; 967 struct dwc3_event_devt devt; 968 struct dwc3_event_gevt gevt; 969 }; 970 971 /** 972 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 973 * parameters 974 * @param2: third parameter 975 * @param1: second parameter 976 * @param0: first parameter 977 */ 978 struct dwc3_gadget_ep_cmd_params { 979 u32 param2; 980 u32 param1; 981 u32 param0; 982 }; 983 984 /* 985 * DWC3 Features to be used as Driver Data 986 */ 987 988 #define DWC3_HAS_PERIPHERAL BIT(0) 989 #define DWC3_HAS_XHCI BIT(1) 990 #define DWC3_HAS_OTG BIT(3) 991 992 /* prototypes */ 993 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 994 int dwc3_init(struct dwc3 *dwc); 995 void dwc3_remove(struct dwc3 *dwc); 996 997 #ifdef CONFIG_USB_DWC3_HOST 998 int dwc3_host_init(struct dwc3 *dwc); 999 void dwc3_host_exit(struct dwc3 *dwc); 1000 #else 1001 static inline int dwc3_host_init(struct dwc3 *dwc) 1002 { return 0; } 1003 static inline void dwc3_host_exit(struct dwc3 *dwc) 1004 { } 1005 #endif 1006 1007 #ifdef CONFIG_USB_DWC3_GADGET 1008 int dwc3_gadget_init(struct dwc3 *dwc); 1009 void dwc3_gadget_exit(struct dwc3 *dwc); 1010 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 1011 int dwc3_gadget_get_link_state(struct dwc3 *dwc); 1012 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 1013 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1014 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 1015 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 1016 #else 1017 static inline int dwc3_gadget_init(struct dwc3 *dwc) 1018 { return 0; } 1019 static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1020 { } 1021 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 1022 { return 0; } 1023 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 1024 { return 0; } 1025 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 1026 enum dwc3_link_state state) 1027 { return 0; } 1028 1029 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1030 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 1031 { return 0; } 1032 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 1033 int cmd, u32 param) 1034 { return 0; } 1035 #endif 1036 1037 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1038