1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 * 10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported 11 * to uboot. 12 * 13 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA 14 */ 15 16 #include <common.h> 17 #include <malloc.h> 18 #include <dwc3-uboot.h> 19 #include <asm/dma-mapping.h> 20 #include <linux/ioport.h> 21 22 #include <linux/usb/ch9.h> 23 #include <linux/usb/gadget.h> 24 25 #include "core.h" 26 #include "gadget.h" 27 #include "io.h" 28 29 #include "linux-compat.h" 30 31 static LIST_HEAD(dwc3_list); 32 /* -------------------------------------------------------------------------- */ 33 34 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 35 { 36 u32 reg; 37 38 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 39 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 40 reg |= DWC3_GCTL_PRTCAPDIR(mode); 41 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 42 } 43 44 /** 45 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 46 * @dwc: pointer to our context structure 47 */ 48 static int dwc3_core_soft_reset(struct dwc3 *dwc) 49 { 50 u32 reg; 51 52 /* Before Resetting PHY, put Core in Reset */ 53 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 54 reg |= DWC3_GCTL_CORESOFTRESET; 55 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 56 57 /* Assert USB3 PHY reset */ 58 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 59 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 60 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 61 62 /* Assert USB2 PHY reset */ 63 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 64 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 65 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 66 67 mdelay(100); 68 69 /* Clear USB3 PHY reset */ 70 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 71 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 72 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 73 74 /* Clear USB2 PHY reset */ 75 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 76 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 77 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 78 79 mdelay(100); 80 81 /* After PHYs are stable we can take Core out of reset state */ 82 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 83 reg &= ~DWC3_GCTL_CORESOFTRESET; 84 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 85 86 return 0; 87 } 88 89 /** 90 * dwc3_free_one_event_buffer - Frees one event buffer 91 * @dwc: Pointer to our controller context structure 92 * @evt: Pointer to event buffer to be freed 93 */ 94 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 95 struct dwc3_event_buffer *evt) 96 { 97 dma_free_coherent(evt->buf); 98 } 99 100 /** 101 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 102 * @dwc: Pointer to our controller context structure 103 * @length: size of the event buffer 104 * 105 * Returns a pointer to the allocated event buffer structure on success 106 * otherwise ERR_PTR(errno). 107 */ 108 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 109 unsigned length) 110 { 111 struct dwc3_event_buffer *evt; 112 113 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 114 if (!evt) 115 return ERR_PTR(-ENOMEM); 116 117 evt->dwc = dwc; 118 evt->length = length; 119 evt->buf = dma_alloc_coherent(length, 120 (unsigned long *)&evt->dma); 121 if (!evt->buf) 122 return ERR_PTR(-ENOMEM); 123 124 dwc3_flush_cache((uintptr_t)evt->buf, evt->length); 125 126 return evt; 127 } 128 129 /** 130 * dwc3_free_event_buffers - frees all allocated event buffers 131 * @dwc: Pointer to our controller context structure 132 */ 133 static void dwc3_free_event_buffers(struct dwc3 *dwc) 134 { 135 struct dwc3_event_buffer *evt; 136 int i; 137 138 for (i = 0; i < dwc->num_event_buffers; i++) { 139 evt = dwc->ev_buffs[i]; 140 if (evt) 141 dwc3_free_one_event_buffer(dwc, evt); 142 } 143 } 144 145 /** 146 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 147 * @dwc: pointer to our controller context structure 148 * @length: size of event buffer 149 * 150 * Returns 0 on success otherwise negative errno. In the error case, dwc 151 * may contain some buffers allocated but not all which were requested. 152 */ 153 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 154 { 155 int num; 156 int i; 157 158 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 159 dwc->num_event_buffers = num; 160 161 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE, 162 sizeof(*dwc->ev_buffs) * num); 163 if (!dwc->ev_buffs) 164 return -ENOMEM; 165 166 for (i = 0; i < num; i++) { 167 struct dwc3_event_buffer *evt; 168 169 evt = dwc3_alloc_one_event_buffer(dwc, length); 170 if (IS_ERR(evt)) { 171 dev_err(dwc->dev, "can't allocate event buffer\n"); 172 return PTR_ERR(evt); 173 } 174 dwc->ev_buffs[i] = evt; 175 } 176 177 return 0; 178 } 179 180 /** 181 * dwc3_event_buffers_setup - setup our allocated event buffers 182 * @dwc: pointer to our controller context structure 183 * 184 * Returns 0 on success otherwise negative errno. 185 */ 186 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 187 { 188 struct dwc3_event_buffer *evt; 189 int n; 190 191 for (n = 0; n < dwc->num_event_buffers; n++) { 192 evt = dwc->ev_buffs[n]; 193 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 194 evt->buf, (unsigned long long) evt->dma, 195 evt->length); 196 197 evt->lpos = 0; 198 199 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 200 lower_32_bits(evt->dma)); 201 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 202 upper_32_bits(evt->dma)); 203 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 204 DWC3_GEVNTSIZ_SIZE(evt->length)); 205 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 206 } 207 208 return 0; 209 } 210 211 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 212 { 213 struct dwc3_event_buffer *evt; 214 int n; 215 216 for (n = 0; n < dwc->num_event_buffers; n++) { 217 evt = dwc->ev_buffs[n]; 218 219 evt->lpos = 0; 220 221 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 222 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 223 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 224 | DWC3_GEVNTSIZ_SIZE(0)); 225 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 226 } 227 } 228 229 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 230 { 231 if (!dwc->has_hibernation) 232 return 0; 233 234 if (!dwc->nr_scratch) 235 return 0; 236 237 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 238 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 239 if (!dwc->scratchbuf) 240 return -ENOMEM; 241 242 return 0; 243 } 244 245 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 246 { 247 dma_addr_t scratch_addr; 248 u32 param; 249 int ret; 250 251 if (!dwc->has_hibernation) 252 return 0; 253 254 if (!dwc->nr_scratch) 255 return 0; 256 257 scratch_addr = dma_map_single(dwc->scratchbuf, 258 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 259 DMA_BIDIRECTIONAL); 260 if (dma_mapping_error(dwc->dev, scratch_addr)) { 261 dev_err(dwc->dev, "failed to map scratch buffer\n"); 262 ret = -EFAULT; 263 goto err0; 264 } 265 266 dwc->scratch_addr = scratch_addr; 267 268 param = lower_32_bits(scratch_addr); 269 270 ret = dwc3_send_gadget_generic_command(dwc, 271 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 272 if (ret < 0) 273 goto err1; 274 275 param = upper_32_bits(scratch_addr); 276 277 ret = dwc3_send_gadget_generic_command(dwc, 278 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 279 if (ret < 0) 280 goto err1; 281 282 return 0; 283 284 err1: 285 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 286 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 287 288 err0: 289 return ret; 290 } 291 292 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 293 { 294 if (!dwc->has_hibernation) 295 return; 296 297 if (!dwc->nr_scratch) 298 return; 299 300 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 301 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 302 kfree(dwc->scratchbuf); 303 } 304 305 static void dwc3_core_num_eps(struct dwc3 *dwc) 306 { 307 struct dwc3_hwparams *parms = &dwc->hwparams; 308 309 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 310 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 311 312 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", 313 dwc->num_in_eps, dwc->num_out_eps); 314 } 315 316 static void dwc3_cache_hwparams(struct dwc3 *dwc) 317 { 318 struct dwc3_hwparams *parms = &dwc->hwparams; 319 320 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 321 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 322 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 323 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 324 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 325 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 326 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 327 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 328 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 329 } 330 331 /** 332 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 333 * @dwc: Pointer to our controller context structure 334 */ 335 static void dwc3_phy_setup(struct dwc3 *dwc) 336 { 337 u32 reg; 338 339 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 340 341 /* 342 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 343 * to '0' during coreConsultant configuration. So default value 344 * will be '0' when the core is reset. Application needs to set it 345 * to '1' after the core initialization is completed. 346 */ 347 if (dwc->revision > DWC3_REVISION_194A) 348 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 349 350 if (dwc->u2ss_inp3_quirk) 351 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 352 353 if (dwc->req_p1p2p3_quirk) 354 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 355 356 if (dwc->del_p1p2p3_quirk) 357 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 358 359 if (dwc->del_phy_power_chg_quirk) 360 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 361 362 if (dwc->lfps_filter_quirk) 363 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 364 365 if (dwc->rx_detect_poll_quirk) 366 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 367 368 if (dwc->tx_de_emphasis_quirk) 369 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 370 371 if (dwc->dis_u3_susphy_quirk) 372 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 373 374 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 375 376 mdelay(100); 377 378 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 379 380 /* 381 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 382 * '0' during coreConsultant configuration. So default value will 383 * be '0' when the core is reset. Application needs to set it to 384 * '1' after the core initialization is completed. 385 */ 386 if (dwc->revision > DWC3_REVISION_194A) 387 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 388 389 if (dwc->dis_u2_susphy_quirk) 390 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 391 392 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 393 394 mdelay(100); 395 } 396 397 /** 398 * dwc3_core_init - Low-level initialization of DWC3 Core 399 * @dwc: Pointer to our controller context structure 400 * 401 * Returns 0 on success otherwise negative errno. 402 */ 403 static int dwc3_core_init(struct dwc3 *dwc) 404 { 405 unsigned long timeout; 406 u32 hwparams4 = dwc->hwparams.hwparams4; 407 u32 reg; 408 int ret; 409 410 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 411 /* This should read as U3 followed by revision number */ 412 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { 413 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 414 ret = -ENODEV; 415 goto err0; 416 } 417 dwc->revision = reg; 418 419 /* Handle USB2.0-only core configuration */ 420 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 421 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 422 if (dwc->maximum_speed == USB_SPEED_SUPER) 423 dwc->maximum_speed = USB_SPEED_HIGH; 424 } 425 426 /* issue device SoftReset too */ 427 timeout = 5000; 428 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 429 while (timeout--) { 430 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 431 if (!(reg & DWC3_DCTL_CSFTRST)) 432 break; 433 }; 434 435 if (!timeout) { 436 dev_err(dwc->dev, "Reset Timed Out\n"); 437 ret = -ETIMEDOUT; 438 goto err0; 439 } 440 441 ret = dwc3_core_soft_reset(dwc); 442 if (ret) 443 goto err0; 444 445 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 446 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 447 448 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 449 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 450 /** 451 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 452 * issue which would cause xHCI compliance tests to fail. 453 * 454 * Because of that we cannot enable clock gating on such 455 * configurations. 456 * 457 * Refers to: 458 * 459 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 460 * SOF/ITP Mode Used 461 */ 462 if ((dwc->dr_mode == USB_DR_MODE_HOST || 463 dwc->dr_mode == USB_DR_MODE_OTG) && 464 (dwc->revision >= DWC3_REVISION_210A && 465 dwc->revision <= DWC3_REVISION_250A)) 466 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 467 else 468 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 469 break; 470 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 471 /* enable hibernation here */ 472 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 473 474 /* 475 * REVISIT Enabling this bit so that host-mode hibernation 476 * will work. Device-mode hibernation is not yet implemented. 477 */ 478 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 479 break; 480 default: 481 dev_dbg(dwc->dev, "No power optimization available\n"); 482 } 483 484 /* check if current dwc3 is on simulation board */ 485 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 486 dev_dbg(dwc->dev, "it is on FPGA board\n"); 487 dwc->is_fpga = true; 488 } 489 490 if(dwc->disable_scramble_quirk && !dwc->is_fpga) 491 WARN(true, 492 "disable_scramble cannot be used on non-FPGA builds\n"); 493 494 if (dwc->disable_scramble_quirk && dwc->is_fpga) 495 reg |= DWC3_GCTL_DISSCRAMBLE; 496 else 497 reg &= ~DWC3_GCTL_DISSCRAMBLE; 498 499 if (dwc->u2exit_lfps_quirk) 500 reg |= DWC3_GCTL_U2EXIT_LFPS; 501 502 /* 503 * WORKAROUND: DWC3 revisions <1.90a have a bug 504 * where the device can fail to connect at SuperSpeed 505 * and falls back to high-speed mode which causes 506 * the device to enter a Connect/Disconnect loop 507 */ 508 if (dwc->revision < DWC3_REVISION_190A) 509 reg |= DWC3_GCTL_U2RSTECN; 510 511 dwc3_core_num_eps(dwc); 512 513 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 514 515 dwc3_phy_setup(dwc); 516 517 ret = dwc3_alloc_scratch_buffers(dwc); 518 if (ret) 519 goto err0; 520 521 ret = dwc3_setup_scratch_buffers(dwc); 522 if (ret) 523 goto err1; 524 525 return 0; 526 527 err1: 528 dwc3_free_scratch_buffers(dwc); 529 530 err0: 531 return ret; 532 } 533 534 static void dwc3_core_exit(struct dwc3 *dwc) 535 { 536 dwc3_free_scratch_buffers(dwc); 537 } 538 539 static int dwc3_core_init_mode(struct dwc3 *dwc) 540 { 541 int ret; 542 543 switch (dwc->dr_mode) { 544 case USB_DR_MODE_PERIPHERAL: 545 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 546 ret = dwc3_gadget_init(dwc); 547 if (ret) { 548 dev_err(dev, "failed to initialize gadget\n"); 549 return ret; 550 } 551 break; 552 case USB_DR_MODE_HOST: 553 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 554 ret = dwc3_host_init(dwc); 555 if (ret) { 556 dev_err(dev, "failed to initialize host\n"); 557 return ret; 558 } 559 break; 560 case USB_DR_MODE_OTG: 561 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 562 ret = dwc3_host_init(dwc); 563 if (ret) { 564 dev_err(dev, "failed to initialize host\n"); 565 return ret; 566 } 567 568 ret = dwc3_gadget_init(dwc); 569 if (ret) { 570 dev_err(dev, "failed to initialize gadget\n"); 571 return ret; 572 } 573 break; 574 default: 575 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 576 return -EINVAL; 577 } 578 579 return 0; 580 } 581 582 static void dwc3_core_exit_mode(struct dwc3 *dwc) 583 { 584 switch (dwc->dr_mode) { 585 case USB_DR_MODE_PERIPHERAL: 586 dwc3_gadget_exit(dwc); 587 break; 588 case USB_DR_MODE_HOST: 589 dwc3_host_exit(dwc); 590 break; 591 case USB_DR_MODE_OTG: 592 dwc3_host_exit(dwc); 593 dwc3_gadget_exit(dwc); 594 break; 595 default: 596 /* do nothing */ 597 break; 598 } 599 } 600 601 #define DWC3_ALIGN_MASK (16 - 1) 602 603 /** 604 * dwc3_uboot_init - dwc3 core uboot initialization code 605 * @dwc3_dev: struct dwc3_device containing initialization data 606 * 607 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux 608 * kernel driver). Pointer to dwc3_device should be passed containing 609 * base address and other initialization data. Returns '0' on success and 610 * a negative value on failure. 611 * 612 * Generally called from board_usb_init() implemented in board file. 613 */ 614 int dwc3_uboot_init(struct dwc3_device *dwc3_dev) 615 { 616 struct dwc3 *dwc; 617 struct device *dev = NULL; 618 u8 lpm_nyet_threshold; 619 u8 tx_de_emphasis; 620 u8 hird_threshold; 621 622 int ret; 623 624 void *mem; 625 626 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 627 if (!mem) 628 return -ENOMEM; 629 630 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 631 dwc->mem = mem; 632 633 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base + 634 DWC3_GLOBALS_REGS_START); 635 636 /* default to highest possible threshold */ 637 lpm_nyet_threshold = 0xff; 638 639 /* default to -3.5dB de-emphasis */ 640 tx_de_emphasis = 1; 641 642 /* 643 * default to assert utmi_sleep_n and use maximum allowed HIRD 644 * threshold value of 0b1100 645 */ 646 hird_threshold = 12; 647 648 dwc->maximum_speed = dwc3_dev->maximum_speed; 649 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum; 650 if (dwc3_dev->lpm_nyet_threshold) 651 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold; 652 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend; 653 if (dwc3_dev->hird_threshold) 654 hird_threshold = dwc3_dev->hird_threshold; 655 656 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize; 657 dwc->dr_mode = dwc3_dev->dr_mode; 658 659 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk; 660 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk; 661 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk; 662 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk; 663 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk; 664 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk; 665 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk; 666 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk; 667 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk; 668 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk; 669 670 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk; 671 if (dwc3_dev->tx_de_emphasis) 672 tx_de_emphasis = dwc3_dev->tx_de_emphasis; 673 674 /* default to superspeed if no maximum_speed passed */ 675 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 676 dwc->maximum_speed = USB_SPEED_SUPER; 677 678 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 679 dwc->tx_de_emphasis = tx_de_emphasis; 680 681 dwc->hird_threshold = hird_threshold 682 | (dwc->is_utmi_l1_suspend << 4); 683 684 dwc->index = dwc3_dev->index; 685 686 dwc3_cache_hwparams(dwc); 687 688 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 689 if (ret) { 690 dev_err(dwc->dev, "failed to allocate event buffers\n"); 691 return -ENOMEM; 692 } 693 694 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 695 dwc->dr_mode = USB_DR_MODE_HOST; 696 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 697 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 698 699 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 700 dwc->dr_mode = USB_DR_MODE_OTG; 701 702 ret = dwc3_core_init(dwc); 703 if (ret) { 704 dev_err(dev, "failed to initialize core\n"); 705 goto err0; 706 } 707 708 ret = dwc3_event_buffers_setup(dwc); 709 if (ret) { 710 dev_err(dwc->dev, "failed to setup event buffers\n"); 711 goto err1; 712 } 713 714 ret = dwc3_core_init_mode(dwc); 715 if (ret) 716 goto err2; 717 718 list_add_tail(&dwc->list, &dwc3_list); 719 720 return 0; 721 722 err2: 723 dwc3_event_buffers_cleanup(dwc); 724 725 err1: 726 dwc3_core_exit(dwc); 727 728 err0: 729 dwc3_free_event_buffers(dwc); 730 731 return ret; 732 } 733 734 /** 735 * dwc3_uboot_exit - dwc3 core uboot cleanup code 736 * @index: index of this controller 737 * 738 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc 739 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller 740 * should be passed and should match with the index passed in 741 * dwc3_device during init. 742 * 743 * Generally called from board file. 744 */ 745 void dwc3_uboot_exit(int index) 746 { 747 struct dwc3 *dwc; 748 749 list_for_each_entry(dwc, &dwc3_list, list) { 750 if (dwc->index != index) 751 continue; 752 753 dwc3_core_exit_mode(dwc); 754 dwc3_event_buffers_cleanup(dwc); 755 dwc3_free_event_buffers(dwc); 756 dwc3_core_exit(dwc); 757 list_del(&dwc->list); 758 kfree(dwc->mem); 759 break; 760 } 761 } 762 763 /** 764 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt 765 * @index: index of this controller 766 * 767 * Invokes dwc3 gadget interrupts. 768 * 769 * Generally called from board file. 770 */ 771 void dwc3_uboot_handle_interrupt(int index) 772 { 773 struct dwc3 *dwc = NULL; 774 775 list_for_each_entry(dwc, &dwc3_list, list) { 776 if (dwc->index != index) 777 continue; 778 779 dwc3_gadget_uboot_handle_interrupt(dwc); 780 break; 781 } 782 } 783 784 MODULE_ALIAS("platform:dwc3"); 785 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 786 MODULE_LICENSE("GPL v2"); 787 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 788