1 /** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported 10 * to uboot. 11 * 12 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <common.h> 18 #include <malloc.h> 19 #include <dwc3-uboot.h> 20 #include <asm/dma-mapping.h> 21 #include <linux/ioport.h> 22 23 #include <linux/usb/ch9.h> 24 #include <linux/usb/gadget.h> 25 26 #include "core.h" 27 #include "gadget.h" 28 #include "io.h" 29 30 #include "linux-compat.h" 31 32 static LIST_HEAD(dwc3_list); 33 /* -------------------------------------------------------------------------- */ 34 35 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 36 { 37 u32 reg; 38 39 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 40 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 41 reg |= DWC3_GCTL_PRTCAPDIR(mode); 42 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 43 } 44 45 /** 46 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 47 * @dwc: pointer to our context structure 48 */ 49 static int dwc3_core_soft_reset(struct dwc3 *dwc) 50 { 51 u32 reg; 52 53 /* Before Resetting PHY, put Core in Reset */ 54 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 55 reg |= DWC3_GCTL_CORESOFTRESET; 56 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 57 58 /* Assert USB3 PHY reset */ 59 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 60 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 61 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 62 63 /* Assert USB2 PHY reset */ 64 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 65 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 66 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 67 68 mdelay(100); 69 70 /* Clear USB3 PHY reset */ 71 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 72 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 73 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 74 75 /* Clear USB2 PHY reset */ 76 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 77 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 78 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 79 80 mdelay(100); 81 82 /* After PHYs are stable we can take Core out of reset state */ 83 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 84 reg &= ~DWC3_GCTL_CORESOFTRESET; 85 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 86 87 return 0; 88 } 89 90 /** 91 * dwc3_free_one_event_buffer - Frees one event buffer 92 * @dwc: Pointer to our controller context structure 93 * @evt: Pointer to event buffer to be freed 94 */ 95 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 96 struct dwc3_event_buffer *evt) 97 { 98 dma_free_coherent(evt->buf); 99 } 100 101 /** 102 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 103 * @dwc: Pointer to our controller context structure 104 * @length: size of the event buffer 105 * 106 * Returns a pointer to the allocated event buffer structure on success 107 * otherwise ERR_PTR(errno). 108 */ 109 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 110 unsigned length) 111 { 112 struct dwc3_event_buffer *evt; 113 114 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 115 if (!evt) 116 return ERR_PTR(-ENOMEM); 117 118 evt->dwc = dwc; 119 evt->length = length; 120 evt->buf = dma_alloc_coherent(length, 121 (unsigned long *)&evt->dma); 122 if (!evt->buf) 123 return ERR_PTR(-ENOMEM); 124 125 dwc3_flush_cache((uintptr_t)evt->buf, evt->length); 126 127 return evt; 128 } 129 130 /** 131 * dwc3_free_event_buffers - frees all allocated event buffers 132 * @dwc: Pointer to our controller context structure 133 */ 134 static void dwc3_free_event_buffers(struct dwc3 *dwc) 135 { 136 struct dwc3_event_buffer *evt; 137 int i; 138 139 for (i = 0; i < dwc->num_event_buffers; i++) { 140 evt = dwc->ev_buffs[i]; 141 if (evt) 142 dwc3_free_one_event_buffer(dwc, evt); 143 } 144 } 145 146 /** 147 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 148 * @dwc: pointer to our controller context structure 149 * @length: size of event buffer 150 * 151 * Returns 0 on success otherwise negative errno. In the error case, dwc 152 * may contain some buffers allocated but not all which were requested. 153 */ 154 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 155 { 156 int num; 157 int i; 158 159 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 160 dwc->num_event_buffers = num; 161 162 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE, 163 sizeof(*dwc->ev_buffs) * num); 164 if (!dwc->ev_buffs) 165 return -ENOMEM; 166 167 for (i = 0; i < num; i++) { 168 struct dwc3_event_buffer *evt; 169 170 evt = dwc3_alloc_one_event_buffer(dwc, length); 171 if (IS_ERR(evt)) { 172 dev_err(dwc->dev, "can't allocate event buffer\n"); 173 return PTR_ERR(evt); 174 } 175 dwc->ev_buffs[i] = evt; 176 } 177 178 return 0; 179 } 180 181 /** 182 * dwc3_event_buffers_setup - setup our allocated event buffers 183 * @dwc: pointer to our controller context structure 184 * 185 * Returns 0 on success otherwise negative errno. 186 */ 187 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 188 { 189 struct dwc3_event_buffer *evt; 190 int n; 191 192 for (n = 0; n < dwc->num_event_buffers; n++) { 193 evt = dwc->ev_buffs[n]; 194 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 195 evt->buf, (unsigned long long) evt->dma, 196 evt->length); 197 198 evt->lpos = 0; 199 200 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 201 lower_32_bits(evt->dma)); 202 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 203 upper_32_bits(evt->dma)); 204 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 205 DWC3_GEVNTSIZ_SIZE(evt->length)); 206 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 207 } 208 209 return 0; 210 } 211 212 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 213 { 214 struct dwc3_event_buffer *evt; 215 int n; 216 217 for (n = 0; n < dwc->num_event_buffers; n++) { 218 evt = dwc->ev_buffs[n]; 219 220 evt->lpos = 0; 221 222 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 223 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 224 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 225 | DWC3_GEVNTSIZ_SIZE(0)); 226 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 227 } 228 } 229 230 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 231 { 232 if (!dwc->has_hibernation) 233 return 0; 234 235 if (!dwc->nr_scratch) 236 return 0; 237 238 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 239 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 240 if (!dwc->scratchbuf) 241 return -ENOMEM; 242 243 return 0; 244 } 245 246 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 247 { 248 dma_addr_t scratch_addr; 249 u32 param; 250 int ret; 251 252 if (!dwc->has_hibernation) 253 return 0; 254 255 if (!dwc->nr_scratch) 256 return 0; 257 258 scratch_addr = dma_map_single(dwc->scratchbuf, 259 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 260 DMA_BIDIRECTIONAL); 261 if (dma_mapping_error(dwc->dev, scratch_addr)) { 262 dev_err(dwc->dev, "failed to map scratch buffer\n"); 263 ret = -EFAULT; 264 goto err0; 265 } 266 267 dwc->scratch_addr = scratch_addr; 268 269 param = lower_32_bits(scratch_addr); 270 271 ret = dwc3_send_gadget_generic_command(dwc, 272 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 273 if (ret < 0) 274 goto err1; 275 276 param = upper_32_bits(scratch_addr); 277 278 ret = dwc3_send_gadget_generic_command(dwc, 279 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 280 if (ret < 0) 281 goto err1; 282 283 return 0; 284 285 err1: 286 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 287 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 288 289 err0: 290 return ret; 291 } 292 293 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 294 { 295 if (!dwc->has_hibernation) 296 return; 297 298 if (!dwc->nr_scratch) 299 return; 300 301 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 302 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 303 kfree(dwc->scratchbuf); 304 } 305 306 static void dwc3_core_num_eps(struct dwc3 *dwc) 307 { 308 struct dwc3_hwparams *parms = &dwc->hwparams; 309 310 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 311 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 312 313 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", 314 dwc->num_in_eps, dwc->num_out_eps); 315 } 316 317 static void dwc3_cache_hwparams(struct dwc3 *dwc) 318 { 319 struct dwc3_hwparams *parms = &dwc->hwparams; 320 321 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 322 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 323 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 324 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 325 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 326 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 327 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 328 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 329 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 330 } 331 332 /** 333 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 334 * @dwc: Pointer to our controller context structure 335 */ 336 static void dwc3_phy_setup(struct dwc3 *dwc) 337 { 338 u32 reg; 339 340 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 341 342 /* 343 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 344 * to '0' during coreConsultant configuration. So default value 345 * will be '0' when the core is reset. Application needs to set it 346 * to '1' after the core initialization is completed. 347 */ 348 if (dwc->revision > DWC3_REVISION_194A) 349 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 350 351 if (dwc->u2ss_inp3_quirk) 352 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 353 354 if (dwc->req_p1p2p3_quirk) 355 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 356 357 if (dwc->del_p1p2p3_quirk) 358 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 359 360 if (dwc->del_phy_power_chg_quirk) 361 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 362 363 if (dwc->lfps_filter_quirk) 364 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 365 366 if (dwc->rx_detect_poll_quirk) 367 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 368 369 if (dwc->tx_de_emphasis_quirk) 370 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 371 372 if (dwc->dis_u3_susphy_quirk) 373 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 374 375 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 376 377 mdelay(100); 378 379 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 380 381 /* 382 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 383 * '0' during coreConsultant configuration. So default value will 384 * be '0' when the core is reset. Application needs to set it to 385 * '1' after the core initialization is completed. 386 */ 387 if (dwc->revision > DWC3_REVISION_194A) 388 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 389 390 if (dwc->dis_u2_susphy_quirk) 391 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 392 393 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 394 395 mdelay(100); 396 } 397 398 /** 399 * dwc3_core_init - Low-level initialization of DWC3 Core 400 * @dwc: Pointer to our controller context structure 401 * 402 * Returns 0 on success otherwise negative errno. 403 */ 404 static int dwc3_core_init(struct dwc3 *dwc) 405 { 406 unsigned long timeout; 407 u32 hwparams4 = dwc->hwparams.hwparams4; 408 u32 reg; 409 int ret; 410 411 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 412 /* This should read as U3 followed by revision number */ 413 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { 414 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 415 ret = -ENODEV; 416 goto err0; 417 } 418 dwc->revision = reg; 419 420 /* Handle USB2.0-only core configuration */ 421 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 422 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 423 if (dwc->maximum_speed == USB_SPEED_SUPER) 424 dwc->maximum_speed = USB_SPEED_HIGH; 425 } 426 427 /* issue device SoftReset too */ 428 timeout = 5000; 429 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 430 while (timeout--) { 431 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 432 if (!(reg & DWC3_DCTL_CSFTRST)) 433 break; 434 }; 435 436 if (!timeout) { 437 dev_err(dwc->dev, "Reset Timed Out\n"); 438 ret = -ETIMEDOUT; 439 goto err0; 440 } 441 442 ret = dwc3_core_soft_reset(dwc); 443 if (ret) 444 goto err0; 445 446 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 447 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 448 449 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 450 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 451 /** 452 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 453 * issue which would cause xHCI compliance tests to fail. 454 * 455 * Because of that we cannot enable clock gating on such 456 * configurations. 457 * 458 * Refers to: 459 * 460 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 461 * SOF/ITP Mode Used 462 */ 463 if ((dwc->dr_mode == USB_DR_MODE_HOST || 464 dwc->dr_mode == USB_DR_MODE_OTG) && 465 (dwc->revision >= DWC3_REVISION_210A && 466 dwc->revision <= DWC3_REVISION_250A)) 467 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 468 else 469 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 470 break; 471 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 472 /* enable hibernation here */ 473 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 474 475 /* 476 * REVISIT Enabling this bit so that host-mode hibernation 477 * will work. Device-mode hibernation is not yet implemented. 478 */ 479 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 480 break; 481 default: 482 dev_dbg(dwc->dev, "No power optimization available\n"); 483 } 484 485 /* check if current dwc3 is on simulation board */ 486 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 487 dev_dbg(dwc->dev, "it is on FPGA board\n"); 488 dwc->is_fpga = true; 489 } 490 491 if(dwc->disable_scramble_quirk && !dwc->is_fpga) 492 WARN(true, 493 "disable_scramble cannot be used on non-FPGA builds\n"); 494 495 if (dwc->disable_scramble_quirk && dwc->is_fpga) 496 reg |= DWC3_GCTL_DISSCRAMBLE; 497 else 498 reg &= ~DWC3_GCTL_DISSCRAMBLE; 499 500 if (dwc->u2exit_lfps_quirk) 501 reg |= DWC3_GCTL_U2EXIT_LFPS; 502 503 /* 504 * WORKAROUND: DWC3 revisions <1.90a have a bug 505 * where the device can fail to connect at SuperSpeed 506 * and falls back to high-speed mode which causes 507 * the device to enter a Connect/Disconnect loop 508 */ 509 if (dwc->revision < DWC3_REVISION_190A) 510 reg |= DWC3_GCTL_U2RSTECN; 511 512 dwc3_core_num_eps(dwc); 513 514 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 515 516 dwc3_phy_setup(dwc); 517 518 ret = dwc3_alloc_scratch_buffers(dwc); 519 if (ret) 520 goto err0; 521 522 ret = dwc3_setup_scratch_buffers(dwc); 523 if (ret) 524 goto err1; 525 526 return 0; 527 528 err1: 529 dwc3_free_scratch_buffers(dwc); 530 531 err0: 532 return ret; 533 } 534 535 static void dwc3_core_exit(struct dwc3 *dwc) 536 { 537 dwc3_free_scratch_buffers(dwc); 538 } 539 540 static int dwc3_core_init_mode(struct dwc3 *dwc) 541 { 542 int ret; 543 544 switch (dwc->dr_mode) { 545 case USB_DR_MODE_PERIPHERAL: 546 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 547 ret = dwc3_gadget_init(dwc); 548 if (ret) { 549 dev_err(dev, "failed to initialize gadget\n"); 550 return ret; 551 } 552 break; 553 case USB_DR_MODE_HOST: 554 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 555 ret = dwc3_host_init(dwc); 556 if (ret) { 557 dev_err(dev, "failed to initialize host\n"); 558 return ret; 559 } 560 break; 561 case USB_DR_MODE_OTG: 562 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 563 ret = dwc3_host_init(dwc); 564 if (ret) { 565 dev_err(dev, "failed to initialize host\n"); 566 return ret; 567 } 568 569 ret = dwc3_gadget_init(dwc); 570 if (ret) { 571 dev_err(dev, "failed to initialize gadget\n"); 572 return ret; 573 } 574 break; 575 default: 576 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 577 return -EINVAL; 578 } 579 580 return 0; 581 } 582 583 static void dwc3_core_exit_mode(struct dwc3 *dwc) 584 { 585 switch (dwc->dr_mode) { 586 case USB_DR_MODE_PERIPHERAL: 587 dwc3_gadget_exit(dwc); 588 break; 589 case USB_DR_MODE_HOST: 590 dwc3_host_exit(dwc); 591 break; 592 case USB_DR_MODE_OTG: 593 dwc3_host_exit(dwc); 594 dwc3_gadget_exit(dwc); 595 break; 596 default: 597 /* do nothing */ 598 break; 599 } 600 } 601 602 #define DWC3_ALIGN_MASK (16 - 1) 603 604 /** 605 * dwc3_uboot_init - dwc3 core uboot initialization code 606 * @dwc3_dev: struct dwc3_device containing initialization data 607 * 608 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux 609 * kernel driver). Pointer to dwc3_device should be passed containing 610 * base address and other initialization data. Returns '0' on success and 611 * a negative value on failure. 612 * 613 * Generally called from board_usb_init() implemented in board file. 614 */ 615 int dwc3_uboot_init(struct dwc3_device *dwc3_dev) 616 { 617 struct dwc3 *dwc; 618 struct device *dev = NULL; 619 u8 lpm_nyet_threshold; 620 u8 tx_de_emphasis; 621 u8 hird_threshold; 622 623 int ret; 624 625 void *mem; 626 627 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 628 if (!mem) 629 return -ENOMEM; 630 631 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 632 dwc->mem = mem; 633 634 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base + 635 DWC3_GLOBALS_REGS_START); 636 637 /* default to highest possible threshold */ 638 lpm_nyet_threshold = 0xff; 639 640 /* default to -3.5dB de-emphasis */ 641 tx_de_emphasis = 1; 642 643 /* 644 * default to assert utmi_sleep_n and use maximum allowed HIRD 645 * threshold value of 0b1100 646 */ 647 hird_threshold = 12; 648 649 dwc->maximum_speed = dwc3_dev->maximum_speed; 650 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum; 651 if (dwc3_dev->lpm_nyet_threshold) 652 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold; 653 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend; 654 if (dwc3_dev->hird_threshold) 655 hird_threshold = dwc3_dev->hird_threshold; 656 657 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize; 658 dwc->dr_mode = dwc3_dev->dr_mode; 659 660 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk; 661 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk; 662 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk; 663 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk; 664 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk; 665 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk; 666 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk; 667 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk; 668 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk; 669 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk; 670 671 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk; 672 if (dwc3_dev->tx_de_emphasis) 673 tx_de_emphasis = dwc3_dev->tx_de_emphasis; 674 675 /* default to superspeed if no maximum_speed passed */ 676 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 677 dwc->maximum_speed = USB_SPEED_SUPER; 678 679 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 680 dwc->tx_de_emphasis = tx_de_emphasis; 681 682 dwc->hird_threshold = hird_threshold 683 | (dwc->is_utmi_l1_suspend << 4); 684 685 dwc->index = dwc3_dev->index; 686 687 dwc3_cache_hwparams(dwc); 688 689 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 690 if (ret) { 691 dev_err(dwc->dev, "failed to allocate event buffers\n"); 692 return -ENOMEM; 693 } 694 695 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 696 dwc->dr_mode = USB_DR_MODE_HOST; 697 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 698 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 699 700 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 701 dwc->dr_mode = USB_DR_MODE_OTG; 702 703 ret = dwc3_core_init(dwc); 704 if (ret) { 705 dev_err(dev, "failed to initialize core\n"); 706 goto err0; 707 } 708 709 ret = dwc3_event_buffers_setup(dwc); 710 if (ret) { 711 dev_err(dwc->dev, "failed to setup event buffers\n"); 712 goto err1; 713 } 714 715 ret = dwc3_core_init_mode(dwc); 716 if (ret) 717 goto err2; 718 719 list_add_tail(&dwc->list, &dwc3_list); 720 721 return 0; 722 723 err2: 724 dwc3_event_buffers_cleanup(dwc); 725 726 err1: 727 dwc3_core_exit(dwc); 728 729 err0: 730 dwc3_free_event_buffers(dwc); 731 732 return ret; 733 } 734 735 /** 736 * dwc3_uboot_exit - dwc3 core uboot cleanup code 737 * @index: index of this controller 738 * 739 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc 740 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller 741 * should be passed and should match with the index passed in 742 * dwc3_device during init. 743 * 744 * Generally called from board file. 745 */ 746 void dwc3_uboot_exit(int index) 747 { 748 struct dwc3 *dwc; 749 750 list_for_each_entry(dwc, &dwc3_list, list) { 751 if (dwc->index != index) 752 continue; 753 754 dwc3_core_exit_mode(dwc); 755 dwc3_event_buffers_cleanup(dwc); 756 dwc3_free_event_buffers(dwc); 757 dwc3_core_exit(dwc); 758 list_del(&dwc->list); 759 kfree(dwc->mem); 760 break; 761 } 762 } 763 764 /** 765 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt 766 * @index: index of this controller 767 * 768 * Invokes dwc3 gadget interrupts. 769 * 770 * Generally called from board file. 771 */ 772 void dwc3_uboot_handle_interrupt(int index) 773 { 774 struct dwc3 *dwc = NULL; 775 776 list_for_each_entry(dwc, &dwc3_list, list) { 777 if (dwc->index != index) 778 continue; 779 780 dwc3_gadget_uboot_handle_interrupt(dwc); 781 break; 782 } 783 } 784 785 MODULE_ALIAS("platform:dwc3"); 786 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 787 MODULE_LICENSE("GPL v2"); 788 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 789