1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * TSC calibration codes are adapted from Linux kernel 5 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <malloc.h> 13 #include <timer.h> 14 #include <asm/cpu.h> 15 #include <asm/io.h> 16 #include <asm/i8254.h> 17 #include <asm/ibmpc.h> 18 #include <asm/msr.h> 19 #include <asm/u-boot-x86.h> 20 21 #define MAX_NUM_FREQS 9 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 /* 26 * According to Intel 64 and IA-32 System Programming Guide, 27 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be 28 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40]. 29 * Unfortunately some Intel Atom SoCs aren't quite compliant to this, 30 * so we need manually differentiate SoC families. This is what the 31 * field msr_plat does. 32 */ 33 struct freq_desc { 34 u8 x86_family; /* CPU family */ 35 u8 x86_model; /* model */ 36 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */ 37 u8 msr_plat; 38 u32 freqs[MAX_NUM_FREQS]; 39 }; 40 41 static struct freq_desc freq_desc_tables[] = { 42 /* PNW */ 43 { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } }, 44 /* CLV+ */ 45 { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } }, 46 /* TNG - Intel Atom processor Z3400 series */ 47 { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } }, 48 /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */ 49 { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } }, 50 /* ANN - Intel Atom processor Z3500 series */ 51 { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } }, 52 /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */ 53 { 6, 0x4c, 1, { 83300, 100000, 133300, 116700, 54 80000, 93300, 90000, 88900, 87500 } }, 55 /* Ivybridge */ 56 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, 57 }; 58 59 static int match_cpu(u8 family, u8 model) 60 { 61 int i; 62 63 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) { 64 if ((family == freq_desc_tables[i].x86_family) && 65 (model == freq_desc_tables[i].x86_model)) 66 return i; 67 } 68 69 return -1; 70 } 71 72 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */ 73 #define id_to_freq(cpu_index, freq_id) \ 74 (freq_desc_tables[cpu_index].freqs[freq_id]) 75 76 /* 77 * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is 78 * reliable and the frequency is known (provided by HW). 79 * 80 * On these platforms PIT/HPET is generally not available so calibration won't 81 * work at all and there is no other clocksource to act as a watchdog for the 82 * TSC, so we have no other choice than to trust it. 83 * 84 * Returns the TSC frequency in MHz or 0 if HW does not provide it. 85 */ 86 static unsigned long __maybe_unused cpu_mhz_from_msr(void) 87 { 88 u32 lo, hi, ratio, freq_id, freq; 89 unsigned long res; 90 int cpu_index; 91 92 if (gd->arch.x86_vendor != X86_VENDOR_INTEL) 93 return 0; 94 95 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model); 96 if (cpu_index < 0) 97 return 0; 98 99 if (freq_desc_tables[cpu_index].msr_plat) { 100 rdmsr(MSR_PLATFORM_INFO, lo, hi); 101 ratio = (lo >> 8) & 0xff; 102 } else { 103 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); 104 ratio = (hi >> 8) & 0x1f; 105 } 106 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio); 107 108 if (freq_desc_tables[cpu_index].msr_plat == 2) { 109 /* TODO: Figure out how best to deal with this */ 110 freq = 100000; 111 debug("Using frequency: %u KHz\n", freq); 112 } else { 113 /* Get FSB FREQ ID */ 114 rdmsr(MSR_FSB_FREQ, lo, hi); 115 freq_id = lo & 0x7; 116 freq = id_to_freq(cpu_index, freq_id); 117 debug("Resolved frequency ID: %u, frequency: %u KHz\n", 118 freq_id, freq); 119 } 120 121 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ 122 res = freq * ratio / 1000; 123 debug("TSC runs at %lu MHz\n", res); 124 125 return res; 126 } 127 128 /* 129 * This reads the current MSB of the PIT counter, and 130 * checks if we are running on sufficiently fast and 131 * non-virtualized hardware. 132 * 133 * Our expectations are: 134 * 135 * - the PIT is running at roughly 1.19MHz 136 * 137 * - each IO is going to take about 1us on real hardware, 138 * but we allow it to be much faster (by a factor of 10) or 139 * _slightly_ slower (ie we allow up to a 2us read+counter 140 * update - anything else implies a unacceptably slow CPU 141 * or PIT for the fast calibration to work. 142 * 143 * - with 256 PIT ticks to read the value, we have 214us to 144 * see the same MSB (and overhead like doing a single TSC 145 * read per MSB value etc). 146 * 147 * - We're doing 2 reads per loop (LSB, MSB), and we expect 148 * them each to take about a microsecond on real hardware. 149 * So we expect a count value of around 100. But we'll be 150 * generous, and accept anything over 50. 151 * 152 * - if the PIT is stuck, and we see *many* more reads, we 153 * return early (and the next caller of pit_expect_msb() 154 * then consider it a failure when they don't see the 155 * next expected value). 156 * 157 * These expectations mean that we know that we have seen the 158 * transition from one expected value to another with a fairly 159 * high accuracy, and we didn't miss any events. We can thus 160 * use the TSC value at the transitions to calculate a pretty 161 * good value for the TSC frequencty. 162 */ 163 static inline int pit_verify_msb(unsigned char val) 164 { 165 /* Ignore LSB */ 166 inb(0x42); 167 return inb(0x42) == val; 168 } 169 170 static inline int pit_expect_msb(unsigned char val, u64 *tscp, 171 unsigned long *deltap) 172 { 173 int count; 174 u64 tsc = 0, prev_tsc = 0; 175 176 for (count = 0; count < 50000; count++) { 177 if (!pit_verify_msb(val)) 178 break; 179 prev_tsc = tsc; 180 tsc = rdtsc(); 181 } 182 *deltap = rdtsc() - prev_tsc; 183 *tscp = tsc; 184 185 /* 186 * We require _some_ success, but the quality control 187 * will be based on the error terms on the TSC values. 188 */ 189 return count > 5; 190 } 191 192 /* 193 * How many MSB values do we want to see? We aim for 194 * a maximum error rate of 500ppm (in practice the 195 * real error is much smaller), but refuse to spend 196 * more than 50ms on it. 197 */ 198 #define MAX_QUICK_PIT_MS 50 199 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) 200 201 static unsigned long __maybe_unused quick_pit_calibrate(void) 202 { 203 int i; 204 u64 tsc, delta; 205 unsigned long d1, d2; 206 207 /* Set the Gate high, disable speaker */ 208 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 209 210 /* 211 * Counter 2, mode 0 (one-shot), binary count 212 * 213 * NOTE! Mode 2 decrements by two (and then the 214 * output is flipped each time, giving the same 215 * final output frequency as a decrement-by-one), 216 * so mode 0 is much better when looking at the 217 * individual counts. 218 */ 219 outb(0xb0, 0x43); 220 221 /* Start at 0xffff */ 222 outb(0xff, 0x42); 223 outb(0xff, 0x42); 224 225 /* 226 * The PIT starts counting at the next edge, so we 227 * need to delay for a microsecond. The easiest way 228 * to do that is to just read back the 16-bit counter 229 * once from the PIT. 230 */ 231 pit_verify_msb(0); 232 233 if (pit_expect_msb(0xff, &tsc, &d1)) { 234 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { 235 if (!pit_expect_msb(0xff-i, &delta, &d2)) 236 break; 237 238 /* 239 * Iterate until the error is less than 500 ppm 240 */ 241 delta -= tsc; 242 if (d1+d2 >= delta >> 11) 243 continue; 244 245 /* 246 * Check the PIT one more time to verify that 247 * all TSC reads were stable wrt the PIT. 248 * 249 * This also guarantees serialization of the 250 * last cycle read ('d2') in pit_expect_msb. 251 */ 252 if (!pit_verify_msb(0xfe - i)) 253 break; 254 goto success; 255 } 256 } 257 debug("Fast TSC calibration failed\n"); 258 return 0; 259 260 success: 261 /* 262 * Ok, if we get here, then we've seen the 263 * MSB of the PIT decrement 'i' times, and the 264 * error has shrunk to less than 500 ppm. 265 * 266 * As a result, we can depend on there not being 267 * any odd delays anywhere, and the TSC reads are 268 * reliable (within the error). 269 * 270 * kHz = ticks / time-in-seconds / 1000; 271 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 272 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) 273 */ 274 delta *= PIT_TICK_RATE; 275 delta /= (i*256*1000); 276 debug("Fast TSC calibration using PIT\n"); 277 return delta / 1000; 278 } 279 280 /* Get the speed of the TSC timer in MHz */ 281 unsigned notrace long get_tbclk_mhz(void) 282 { 283 return get_tbclk() / 1000000; 284 } 285 286 static ulong get_ms_timer(void) 287 { 288 return (get_ticks() * 1000) / get_tbclk(); 289 } 290 291 ulong get_timer(ulong base) 292 { 293 return get_ms_timer() - base; 294 } 295 296 ulong notrace timer_get_us(void) 297 { 298 return get_ticks() / get_tbclk_mhz(); 299 } 300 301 ulong timer_get_boot_us(void) 302 { 303 return timer_get_us(); 304 } 305 306 void __udelay(unsigned long usec) 307 { 308 u64 now = get_ticks(); 309 u64 stop; 310 311 stop = now + usec * get_tbclk_mhz(); 312 313 while ((int64_t)(stop - get_ticks()) > 0) 314 #if defined(CONFIG_QEMU) && defined(CONFIG_SMP) 315 /* 316 * Add a 'pause' instruction on qemu target, 317 * to give other VCPUs a chance to run. 318 */ 319 asm volatile("pause"); 320 #else 321 ; 322 #endif 323 } 324 325 static int tsc_timer_get_count(struct udevice *dev, u64 *count) 326 { 327 u64 now_tick = rdtsc(); 328 329 *count = now_tick - gd->arch.tsc_base; 330 331 return 0; 332 } 333 334 static void tsc_timer_ensure_setup(void) 335 { 336 if (gd->arch.tsc_base) 337 return; 338 gd->arch.tsc_base = rdtsc(); 339 340 /* 341 * If there is no clock frequency specified in the device tree, 342 * calibrate it by ourselves. 343 */ 344 if (!gd->arch.clock_rate) { 345 unsigned long fast_calibrate; 346 347 fast_calibrate = cpu_mhz_from_msr(); 348 if (!fast_calibrate) { 349 fast_calibrate = quick_pit_calibrate(); 350 if (!fast_calibrate) 351 panic("TSC frequency is ZERO"); 352 } 353 354 gd->arch.clock_rate = fast_calibrate * 1000000; 355 } 356 } 357 358 static int tsc_timer_probe(struct udevice *dev) 359 { 360 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); 361 362 tsc_timer_ensure_setup(); 363 uc_priv->clock_rate = gd->arch.clock_rate; 364 365 return 0; 366 } 367 368 unsigned long notrace timer_early_get_rate(void) 369 { 370 tsc_timer_ensure_setup(); 371 372 return gd->arch.clock_rate; 373 } 374 375 u64 notrace timer_early_get_count(void) 376 { 377 return rdtsc() - gd->arch.tsc_base; 378 } 379 380 static const struct timer_ops tsc_timer_ops = { 381 .get_count = tsc_timer_get_count, 382 }; 383 384 static const struct udevice_id tsc_timer_ids[] = { 385 { .compatible = "x86,tsc-timer", }, 386 { } 387 }; 388 389 U_BOOT_DRIVER(tsc_timer) = { 390 .name = "tsc_timer", 391 .id = UCLASS_TIMER, 392 .of_match = tsc_timer_ids, 393 .probe = tsc_timer_probe, 394 .ops = &tsc_timer_ops, 395 .flags = DM_FLAG_PRE_RELOC, 396 }; 397