1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * TSC calibration codes are adapted from Linux kernel 5 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <malloc.h> 13 #include <timer.h> 14 #include <asm/cpu.h> 15 #include <asm/io.h> 16 #include <asm/i8254.h> 17 #include <asm/ibmpc.h> 18 #include <asm/msr.h> 19 #include <asm/u-boot-x86.h> 20 21 #define MAX_NUM_FREQS 8 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 /* 26 * According to Intel 64 and IA-32 System Programming Guide, 27 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be 28 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40]. 29 * Unfortunately some Intel Atom SoCs aren't quite compliant to this, 30 * so we need manually differentiate SoC families. This is what the 31 * field msr_plat does. 32 */ 33 struct freq_desc { 34 u8 x86_family; /* CPU family */ 35 u8 x86_model; /* model */ 36 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */ 37 u8 msr_plat; 38 u32 freqs[MAX_NUM_FREQS]; 39 }; 40 41 static struct freq_desc freq_desc_tables[] = { 42 /* PNW */ 43 { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } }, 44 /* CLV+ */ 45 { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } }, 46 /* TNG - Intel Atom processor Z3400 series */ 47 { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } }, 48 /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */ 49 { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } }, 50 /* ANN - Intel Atom processor Z3500 series */ 51 { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } }, 52 /* Ivybridge */ 53 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } }, 54 }; 55 56 static int match_cpu(u8 family, u8 model) 57 { 58 int i; 59 60 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) { 61 if ((family == freq_desc_tables[i].x86_family) && 62 (model == freq_desc_tables[i].x86_model)) 63 return i; 64 } 65 66 return -1; 67 } 68 69 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */ 70 #define id_to_freq(cpu_index, freq_id) \ 71 (freq_desc_tables[cpu_index].freqs[freq_id]) 72 73 /* 74 * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is 75 * reliable and the frequency is known (provided by HW). 76 * 77 * On these platforms PIT/HPET is generally not available so calibration won't 78 * work at all and there is no other clocksource to act as a watchdog for the 79 * TSC, so we have no other choice than to trust it. 80 * 81 * Returns the TSC frequency in MHz or 0 if HW does not provide it. 82 */ 83 static unsigned long __maybe_unused cpu_mhz_from_msr(void) 84 { 85 u32 lo, hi, ratio, freq_id, freq; 86 unsigned long res; 87 int cpu_index; 88 89 if (gd->arch.x86_vendor != X86_VENDOR_INTEL) 90 return 0; 91 92 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model); 93 if (cpu_index < 0) 94 return 0; 95 96 if (freq_desc_tables[cpu_index].msr_plat) { 97 rdmsr(MSR_PLATFORM_INFO, lo, hi); 98 ratio = (lo >> 8) & 0xff; 99 } else { 100 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); 101 ratio = (hi >> 8) & 0x1f; 102 } 103 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio); 104 105 if (freq_desc_tables[cpu_index].msr_plat == 2) { 106 /* TODO: Figure out how best to deal with this */ 107 freq = 100000; 108 debug("Using frequency: %u KHz\n", freq); 109 } else { 110 /* Get FSB FREQ ID */ 111 rdmsr(MSR_FSB_FREQ, lo, hi); 112 freq_id = lo & 0x7; 113 freq = id_to_freq(cpu_index, freq_id); 114 debug("Resolved frequency ID: %u, frequency: %u KHz\n", 115 freq_id, freq); 116 } 117 118 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ 119 res = freq * ratio / 1000; 120 debug("TSC runs at %lu MHz\n", res); 121 122 return res; 123 } 124 125 /* 126 * This reads the current MSB of the PIT counter, and 127 * checks if we are running on sufficiently fast and 128 * non-virtualized hardware. 129 * 130 * Our expectations are: 131 * 132 * - the PIT is running at roughly 1.19MHz 133 * 134 * - each IO is going to take about 1us on real hardware, 135 * but we allow it to be much faster (by a factor of 10) or 136 * _slightly_ slower (ie we allow up to a 2us read+counter 137 * update - anything else implies a unacceptably slow CPU 138 * or PIT for the fast calibration to work. 139 * 140 * - with 256 PIT ticks to read the value, we have 214us to 141 * see the same MSB (and overhead like doing a single TSC 142 * read per MSB value etc). 143 * 144 * - We're doing 2 reads per loop (LSB, MSB), and we expect 145 * them each to take about a microsecond on real hardware. 146 * So we expect a count value of around 100. But we'll be 147 * generous, and accept anything over 50. 148 * 149 * - if the PIT is stuck, and we see *many* more reads, we 150 * return early (and the next caller of pit_expect_msb() 151 * then consider it a failure when they don't see the 152 * next expected value). 153 * 154 * These expectations mean that we know that we have seen the 155 * transition from one expected value to another with a fairly 156 * high accuracy, and we didn't miss any events. We can thus 157 * use the TSC value at the transitions to calculate a pretty 158 * good value for the TSC frequencty. 159 */ 160 static inline int pit_verify_msb(unsigned char val) 161 { 162 /* Ignore LSB */ 163 inb(0x42); 164 return inb(0x42) == val; 165 } 166 167 static inline int pit_expect_msb(unsigned char val, u64 *tscp, 168 unsigned long *deltap) 169 { 170 int count; 171 u64 tsc = 0, prev_tsc = 0; 172 173 for (count = 0; count < 50000; count++) { 174 if (!pit_verify_msb(val)) 175 break; 176 prev_tsc = tsc; 177 tsc = rdtsc(); 178 } 179 *deltap = rdtsc() - prev_tsc; 180 *tscp = tsc; 181 182 /* 183 * We require _some_ success, but the quality control 184 * will be based on the error terms on the TSC values. 185 */ 186 return count > 5; 187 } 188 189 /* 190 * How many MSB values do we want to see? We aim for 191 * a maximum error rate of 500ppm (in practice the 192 * real error is much smaller), but refuse to spend 193 * more than 50ms on it. 194 */ 195 #define MAX_QUICK_PIT_MS 50 196 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) 197 198 static unsigned long __maybe_unused quick_pit_calibrate(void) 199 { 200 int i; 201 u64 tsc, delta; 202 unsigned long d1, d2; 203 204 /* Set the Gate high, disable speaker */ 205 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 206 207 /* 208 * Counter 2, mode 0 (one-shot), binary count 209 * 210 * NOTE! Mode 2 decrements by two (and then the 211 * output is flipped each time, giving the same 212 * final output frequency as a decrement-by-one), 213 * so mode 0 is much better when looking at the 214 * individual counts. 215 */ 216 outb(0xb0, 0x43); 217 218 /* Start at 0xffff */ 219 outb(0xff, 0x42); 220 outb(0xff, 0x42); 221 222 /* 223 * The PIT starts counting at the next edge, so we 224 * need to delay for a microsecond. The easiest way 225 * to do that is to just read back the 16-bit counter 226 * once from the PIT. 227 */ 228 pit_verify_msb(0); 229 230 if (pit_expect_msb(0xff, &tsc, &d1)) { 231 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { 232 if (!pit_expect_msb(0xff-i, &delta, &d2)) 233 break; 234 235 /* 236 * Iterate until the error is less than 500 ppm 237 */ 238 delta -= tsc; 239 if (d1+d2 >= delta >> 11) 240 continue; 241 242 /* 243 * Check the PIT one more time to verify that 244 * all TSC reads were stable wrt the PIT. 245 * 246 * This also guarantees serialization of the 247 * last cycle read ('d2') in pit_expect_msb. 248 */ 249 if (!pit_verify_msb(0xfe - i)) 250 break; 251 goto success; 252 } 253 } 254 debug("Fast TSC calibration failed\n"); 255 return 0; 256 257 success: 258 /* 259 * Ok, if we get here, then we've seen the 260 * MSB of the PIT decrement 'i' times, and the 261 * error has shrunk to less than 500 ppm. 262 * 263 * As a result, we can depend on there not being 264 * any odd delays anywhere, and the TSC reads are 265 * reliable (within the error). 266 * 267 * kHz = ticks / time-in-seconds / 1000; 268 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 269 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) 270 */ 271 delta *= PIT_TICK_RATE; 272 delta /= (i*256*1000); 273 debug("Fast TSC calibration using PIT\n"); 274 return delta / 1000; 275 } 276 277 /* Get the speed of the TSC timer in MHz */ 278 unsigned notrace long get_tbclk_mhz(void) 279 { 280 return get_tbclk() / 1000000; 281 } 282 283 static ulong get_ms_timer(void) 284 { 285 return (get_ticks() * 1000) / get_tbclk(); 286 } 287 288 ulong get_timer(ulong base) 289 { 290 return get_ms_timer() - base; 291 } 292 293 ulong notrace timer_get_us(void) 294 { 295 return get_ticks() / get_tbclk_mhz(); 296 } 297 298 ulong timer_get_boot_us(void) 299 { 300 return timer_get_us(); 301 } 302 303 void __udelay(unsigned long usec) 304 { 305 u64 now = get_ticks(); 306 u64 stop; 307 308 stop = now + usec * get_tbclk_mhz(); 309 310 while ((int64_t)(stop - get_ticks()) > 0) 311 #if defined(CONFIG_QEMU) && defined(CONFIG_SMP) 312 /* 313 * Add a 'pause' instruction on qemu target, 314 * to give other VCPUs a chance to run. 315 */ 316 asm volatile("pause"); 317 #else 318 ; 319 #endif 320 } 321 322 static int tsc_timer_get_count(struct udevice *dev, u64 *count) 323 { 324 u64 now_tick = rdtsc(); 325 326 *count = now_tick - gd->arch.tsc_base; 327 328 return 0; 329 } 330 331 static int tsc_timer_probe(struct udevice *dev) 332 { 333 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); 334 335 gd->arch.tsc_base = rdtsc(); 336 337 /* 338 * If there is no clock frequency specified in the device tree, 339 * calibrate it by ourselves. 340 */ 341 if (!uc_priv->clock_rate) { 342 unsigned long fast_calibrate; 343 344 fast_calibrate = cpu_mhz_from_msr(); 345 if (!fast_calibrate) { 346 fast_calibrate = quick_pit_calibrate(); 347 if (!fast_calibrate) 348 panic("TSC frequency is ZERO"); 349 } 350 351 uc_priv->clock_rate = fast_calibrate * 1000000; 352 } 353 354 return 0; 355 } 356 357 static const struct timer_ops tsc_timer_ops = { 358 .get_count = tsc_timer_get_count, 359 }; 360 361 static const struct udevice_id tsc_timer_ids[] = { 362 { .compatible = "x86,tsc-timer", }, 363 { } 364 }; 365 366 U_BOOT_DRIVER(tsc_timer) = { 367 .name = "tsc_timer", 368 .id = UCLASS_TIMER, 369 .of_match = tsc_timer_ids, 370 .probe = tsc_timer_probe, 371 .ops = &tsc_timer_ops, 372 .flags = DM_FLAG_PRE_RELOC, 373 }; 374