1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * TSC calibration codes are adapted from Linux kernel 5 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <malloc.h> 13 #include <timer.h> 14 #include <asm/io.h> 15 #include <asm/i8254.h> 16 #include <asm/ibmpc.h> 17 #include <asm/msr.h> 18 #include <asm/u-boot-x86.h> 19 20 /* CPU reference clock frequency: in KHz */ 21 #define FREQ_83 83200 22 #define FREQ_100 99840 23 #define FREQ_133 133200 24 #define FREQ_166 166400 25 26 #define MAX_NUM_FREQS 8 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 /* 31 * According to Intel 64 and IA-32 System Programming Guide, 32 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be 33 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40]. 34 * Unfortunately some Intel Atom SoCs aren't quite compliant to this, 35 * so we need manually differentiate SoC families. This is what the 36 * field msr_plat does. 37 */ 38 struct freq_desc { 39 u8 x86_family; /* CPU family */ 40 u8 x86_model; /* model */ 41 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */ 42 u8 msr_plat; 43 u32 freqs[MAX_NUM_FREQS]; 44 }; 45 46 static struct freq_desc freq_desc_tables[] = { 47 /* PNW */ 48 { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } }, 49 /* CLV+ */ 50 { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } }, 51 /* TNG */ 52 { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } }, 53 /* VLV2 */ 54 { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } }, 55 /* Ivybridge */ 56 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } }, 57 /* ANN */ 58 { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } }, 59 }; 60 61 static int match_cpu(u8 family, u8 model) 62 { 63 int i; 64 65 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) { 66 if ((family == freq_desc_tables[i].x86_family) && 67 (model == freq_desc_tables[i].x86_model)) 68 return i; 69 } 70 71 return -1; 72 } 73 74 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */ 75 #define id_to_freq(cpu_index, freq_id) \ 76 (freq_desc_tables[cpu_index].freqs[freq_id]) 77 78 /* 79 * Do MSR calibration only for known/supported CPUs. 80 * 81 * Returns the calibration value or 0 if MSR calibration failed. 82 */ 83 static unsigned long __maybe_unused try_msr_calibrate_tsc(void) 84 { 85 u32 lo, hi, ratio, freq_id, freq; 86 unsigned long res; 87 int cpu_index; 88 89 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model); 90 if (cpu_index < 0) 91 return 0; 92 93 if (freq_desc_tables[cpu_index].msr_plat) { 94 rdmsr(MSR_PLATFORM_INFO, lo, hi); 95 ratio = (lo >> 8) & 0x1f; 96 } else { 97 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); 98 ratio = (hi >> 8) & 0x1f; 99 } 100 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio); 101 102 if (!ratio) 103 goto fail; 104 105 if (freq_desc_tables[cpu_index].msr_plat == 2) { 106 /* TODO: Figure out how best to deal with this */ 107 freq = FREQ_100; 108 debug("Using frequency: %u KHz\n", freq); 109 } else { 110 /* Get FSB FREQ ID */ 111 rdmsr(MSR_FSB_FREQ, lo, hi); 112 freq_id = lo & 0x7; 113 freq = id_to_freq(cpu_index, freq_id); 114 debug("Resolved frequency ID: %u, frequency: %u KHz\n", 115 freq_id, freq); 116 } 117 if (!freq) 118 goto fail; 119 120 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ 121 res = freq * ratio / 1000; 122 debug("TSC runs at %lu MHz\n", res); 123 124 return res; 125 126 fail: 127 debug("Fast TSC calibration using MSR failed\n"); 128 return 0; 129 } 130 131 /* 132 * This reads the current MSB of the PIT counter, and 133 * checks if we are running on sufficiently fast and 134 * non-virtualized hardware. 135 * 136 * Our expectations are: 137 * 138 * - the PIT is running at roughly 1.19MHz 139 * 140 * - each IO is going to take about 1us on real hardware, 141 * but we allow it to be much faster (by a factor of 10) or 142 * _slightly_ slower (ie we allow up to a 2us read+counter 143 * update - anything else implies a unacceptably slow CPU 144 * or PIT for the fast calibration to work. 145 * 146 * - with 256 PIT ticks to read the value, we have 214us to 147 * see the same MSB (and overhead like doing a single TSC 148 * read per MSB value etc). 149 * 150 * - We're doing 2 reads per loop (LSB, MSB), and we expect 151 * them each to take about a microsecond on real hardware. 152 * So we expect a count value of around 100. But we'll be 153 * generous, and accept anything over 50. 154 * 155 * - if the PIT is stuck, and we see *many* more reads, we 156 * return early (and the next caller of pit_expect_msb() 157 * then consider it a failure when they don't see the 158 * next expected value). 159 * 160 * These expectations mean that we know that we have seen the 161 * transition from one expected value to another with a fairly 162 * high accuracy, and we didn't miss any events. We can thus 163 * use the TSC value at the transitions to calculate a pretty 164 * good value for the TSC frequencty. 165 */ 166 static inline int pit_verify_msb(unsigned char val) 167 { 168 /* Ignore LSB */ 169 inb(0x42); 170 return inb(0x42) == val; 171 } 172 173 static inline int pit_expect_msb(unsigned char val, u64 *tscp, 174 unsigned long *deltap) 175 { 176 int count; 177 u64 tsc = 0, prev_tsc = 0; 178 179 for (count = 0; count < 50000; count++) { 180 if (!pit_verify_msb(val)) 181 break; 182 prev_tsc = tsc; 183 tsc = rdtsc(); 184 } 185 *deltap = rdtsc() - prev_tsc; 186 *tscp = tsc; 187 188 /* 189 * We require _some_ success, but the quality control 190 * will be based on the error terms on the TSC values. 191 */ 192 return count > 5; 193 } 194 195 /* 196 * How many MSB values do we want to see? We aim for 197 * a maximum error rate of 500ppm (in practice the 198 * real error is much smaller), but refuse to spend 199 * more than 50ms on it. 200 */ 201 #define MAX_QUICK_PIT_MS 50 202 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) 203 204 static unsigned long __maybe_unused quick_pit_calibrate(void) 205 { 206 int i; 207 u64 tsc, delta; 208 unsigned long d1, d2; 209 210 /* Set the Gate high, disable speaker */ 211 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 212 213 /* 214 * Counter 2, mode 0 (one-shot), binary count 215 * 216 * NOTE! Mode 2 decrements by two (and then the 217 * output is flipped each time, giving the same 218 * final output frequency as a decrement-by-one), 219 * so mode 0 is much better when looking at the 220 * individual counts. 221 */ 222 outb(0xb0, 0x43); 223 224 /* Start at 0xffff */ 225 outb(0xff, 0x42); 226 outb(0xff, 0x42); 227 228 /* 229 * The PIT starts counting at the next edge, so we 230 * need to delay for a microsecond. The easiest way 231 * to do that is to just read back the 16-bit counter 232 * once from the PIT. 233 */ 234 pit_verify_msb(0); 235 236 if (pit_expect_msb(0xff, &tsc, &d1)) { 237 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { 238 if (!pit_expect_msb(0xff-i, &delta, &d2)) 239 break; 240 241 /* 242 * Iterate until the error is less than 500 ppm 243 */ 244 delta -= tsc; 245 if (d1+d2 >= delta >> 11) 246 continue; 247 248 /* 249 * Check the PIT one more time to verify that 250 * all TSC reads were stable wrt the PIT. 251 * 252 * This also guarantees serialization of the 253 * last cycle read ('d2') in pit_expect_msb. 254 */ 255 if (!pit_verify_msb(0xfe - i)) 256 break; 257 goto success; 258 } 259 } 260 debug("Fast TSC calibration failed\n"); 261 return 0; 262 263 success: 264 /* 265 * Ok, if we get here, then we've seen the 266 * MSB of the PIT decrement 'i' times, and the 267 * error has shrunk to less than 500 ppm. 268 * 269 * As a result, we can depend on there not being 270 * any odd delays anywhere, and the TSC reads are 271 * reliable (within the error). 272 * 273 * kHz = ticks / time-in-seconds / 1000; 274 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 275 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) 276 */ 277 delta *= PIT_TICK_RATE; 278 delta /= (i*256*1000); 279 debug("Fast TSC calibration using PIT\n"); 280 return delta / 1000; 281 } 282 283 /* Get the speed of the TSC timer in MHz */ 284 unsigned notrace long get_tbclk_mhz(void) 285 { 286 return get_tbclk() / 1000000; 287 } 288 289 static ulong get_ms_timer(void) 290 { 291 return (get_ticks() * 1000) / get_tbclk(); 292 } 293 294 ulong get_timer(ulong base) 295 { 296 return get_ms_timer() - base; 297 } 298 299 ulong notrace timer_get_us(void) 300 { 301 return get_ticks() / get_tbclk_mhz(); 302 } 303 304 ulong timer_get_boot_us(void) 305 { 306 return timer_get_us(); 307 } 308 309 void __udelay(unsigned long usec) 310 { 311 u64 now = get_ticks(); 312 u64 stop; 313 314 stop = now + usec * get_tbclk_mhz(); 315 316 while ((int64_t)(stop - get_ticks()) > 0) 317 #if defined(CONFIG_QEMU) && defined(CONFIG_SMP) 318 /* 319 * Add a 'pause' instruction on qemu target, 320 * to give other VCPUs a chance to run. 321 */ 322 asm volatile("pause"); 323 #else 324 ; 325 #endif 326 } 327 328 static int tsc_timer_get_count(struct udevice *dev, u64 *count) 329 { 330 u64 now_tick = rdtsc(); 331 332 *count = now_tick - gd->arch.tsc_base; 333 334 return 0; 335 } 336 337 static int tsc_timer_probe(struct udevice *dev) 338 { 339 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); 340 341 gd->arch.tsc_base = rdtsc(); 342 343 /* 344 * If there is no clock frequency specified in the device tree, 345 * calibrate it by ourselves. 346 */ 347 if (!uc_priv->clock_rate) { 348 unsigned long fast_calibrate; 349 350 fast_calibrate = try_msr_calibrate_tsc(); 351 if (!fast_calibrate) { 352 fast_calibrate = quick_pit_calibrate(); 353 if (!fast_calibrate) 354 panic("TSC frequency is ZERO"); 355 } 356 357 uc_priv->clock_rate = fast_calibrate * 1000000; 358 } 359 360 return 0; 361 } 362 363 static const struct timer_ops tsc_timer_ops = { 364 .get_count = tsc_timer_get_count, 365 }; 366 367 static const struct udevice_id tsc_timer_ids[] = { 368 { .compatible = "x86,tsc-timer", }, 369 { } 370 }; 371 372 U_BOOT_DRIVER(tsc_timer) = { 373 .name = "tsc_timer", 374 .id = UCLASS_TIMER, 375 .of_match = tsc_timer_ids, 376 .probe = tsc_timer_probe, 377 .ops = &tsc_timer_ops, 378 .flags = DM_FLAG_PRE_RELOC, 379 }; 380