1 /* 2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <fdtdec.h> 12 #include <timer.h> 13 14 #include <asm/io.h> 15 16 /* Timer control1 register */ 17 #define CR1_CEN BIT(0) 18 #define CR1_ARPE BIT(7) 19 20 /* Event Generation Register register */ 21 #define EGR_UG BIT(0) 22 23 /* Auto reload register for free running config */ 24 #define GPT_FREE_RUNNING 0xFFFFFFFF 25 26 struct stm32_timer_regs { 27 u32 cr1; 28 u32 cr2; 29 u32 smcr; 30 u32 dier; 31 u32 sr; 32 u32 egr; 33 u32 ccmr1; 34 u32 ccmr2; 35 u32 ccer; 36 u32 cnt; 37 u32 psc; 38 u32 arr; 39 u32 reserved; 40 u32 ccr1; 41 u32 ccr2; 42 u32 ccr3; 43 u32 ccr4; 44 u32 reserved1; 45 u32 dcr; 46 u32 dmar; 47 u32 tim2_5_or; 48 }; 49 50 struct stm32_timer_priv { 51 struct stm32_timer_regs *base; 52 }; 53 54 static int stm32_timer_get_count(struct udevice *dev, u64 *count) 55 { 56 struct stm32_timer_priv *priv = dev_get_priv(dev); 57 struct stm32_timer_regs *regs = priv->base; 58 59 *count = readl(®s->cnt); 60 61 return 0; 62 } 63 64 static int stm32_timer_probe(struct udevice *dev) 65 { 66 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); 67 struct stm32_timer_priv *priv = dev_get_priv(dev); 68 struct stm32_timer_regs *regs; 69 struct clk clk; 70 fdt_addr_t addr; 71 int ret; 72 u32 rate, psc; 73 74 addr = dev_read_addr(dev); 75 if (addr == FDT_ADDR_T_NONE) 76 return -EINVAL; 77 78 priv->base = (struct stm32_timer_regs *)addr; 79 80 ret = clk_get_by_index(dev, 0, &clk); 81 if (ret < 0) 82 return ret; 83 84 ret = clk_enable(&clk); 85 if (ret) { 86 dev_err(dev, "failed to enable clock\n"); 87 return ret; 88 } 89 90 regs = priv->base; 91 92 /* Stop the timer */ 93 clrbits_le32(®s->cr1, CR1_CEN); 94 95 /* get timer clock */ 96 rate = clk_get_rate(&clk); 97 98 /* we set timer prescaler to obtain a 1MHz timer counter frequency */ 99 psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1; 100 writel(psc, ®s->psc); 101 102 /* Set timer frequency to 1MHz */ 103 uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; 104 105 /* Configure timer for auto-reload */ 106 setbits_le32(®s->cr1, CR1_ARPE); 107 108 /* load value for auto reload */ 109 writel(GPT_FREE_RUNNING, ®s->arr); 110 111 /* start timer */ 112 setbits_le32(®s->cr1, CR1_CEN); 113 114 /* Update generation */ 115 setbits_le32(®s->egr, EGR_UG); 116 117 return 0; 118 } 119 120 static const struct timer_ops stm32_timer_ops = { 121 .get_count = stm32_timer_get_count, 122 }; 123 124 static const struct udevice_id stm32_timer_ids[] = { 125 { .compatible = "st,stm32-timer" }, 126 {} 127 }; 128 129 U_BOOT_DRIVER(stm32_timer) = { 130 .name = "stm32_timer", 131 .id = UCLASS_TIMER, 132 .of_match = stm32_timer_ids, 133 .priv_auto_alloc_size = sizeof(struct stm32_timer_priv), 134 .probe = stm32_timer_probe, 135 .ops = &stm32_timer_ops, 136 .flags = DM_FLAG_PRE_RELOC, 137 }; 138 139