1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <fdtdec.h> 11 #include <timer.h> 12 13 #include <asm/io.h> 14 15 /* Timer control1 register */ 16 #define CR1_CEN BIT(0) 17 #define CR1_ARPE BIT(7) 18 19 /* Event Generation Register register */ 20 #define EGR_UG BIT(0) 21 22 /* Auto reload register for free running config */ 23 #define GPT_FREE_RUNNING 0xFFFFFFFF 24 25 struct stm32_timer_regs { 26 u32 cr1; 27 u32 cr2; 28 u32 smcr; 29 u32 dier; 30 u32 sr; 31 u32 egr; 32 u32 ccmr1; 33 u32 ccmr2; 34 u32 ccer; 35 u32 cnt; 36 u32 psc; 37 u32 arr; 38 u32 reserved; 39 u32 ccr1; 40 u32 ccr2; 41 u32 ccr3; 42 u32 ccr4; 43 u32 reserved1; 44 u32 dcr; 45 u32 dmar; 46 u32 tim2_5_or; 47 }; 48 49 struct stm32_timer_priv { 50 struct stm32_timer_regs *base; 51 }; 52 53 static int stm32_timer_get_count(struct udevice *dev, u64 *count) 54 { 55 struct stm32_timer_priv *priv = dev_get_priv(dev); 56 struct stm32_timer_regs *regs = priv->base; 57 58 *count = readl(®s->cnt); 59 60 return 0; 61 } 62 63 static int stm32_timer_probe(struct udevice *dev) 64 { 65 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); 66 struct stm32_timer_priv *priv = dev_get_priv(dev); 67 struct stm32_timer_regs *regs; 68 struct clk clk; 69 fdt_addr_t addr; 70 int ret; 71 u32 rate, psc; 72 73 addr = dev_read_addr(dev); 74 if (addr == FDT_ADDR_T_NONE) 75 return -EINVAL; 76 77 priv->base = (struct stm32_timer_regs *)addr; 78 79 ret = clk_get_by_index(dev, 0, &clk); 80 if (ret < 0) 81 return ret; 82 83 ret = clk_enable(&clk); 84 if (ret) { 85 dev_err(dev, "failed to enable clock\n"); 86 return ret; 87 } 88 89 regs = priv->base; 90 91 /* Stop the timer */ 92 clrbits_le32(®s->cr1, CR1_CEN); 93 94 /* get timer clock */ 95 rate = clk_get_rate(&clk); 96 97 /* we set timer prescaler to obtain a 1MHz timer counter frequency */ 98 psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1; 99 writel(psc, ®s->psc); 100 101 /* Set timer frequency to 1MHz */ 102 uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; 103 104 /* Configure timer for auto-reload */ 105 setbits_le32(®s->cr1, CR1_ARPE); 106 107 /* load value for auto reload */ 108 writel(GPT_FREE_RUNNING, ®s->arr); 109 110 /* start timer */ 111 setbits_le32(®s->cr1, CR1_CEN); 112 113 /* Update generation */ 114 setbits_le32(®s->egr, EGR_UG); 115 116 return 0; 117 } 118 119 static const struct timer_ops stm32_timer_ops = { 120 .get_count = stm32_timer_get_count, 121 }; 122 123 static const struct udevice_id stm32_timer_ids[] = { 124 { .compatible = "st,stm32-timer" }, 125 {} 126 }; 127 128 U_BOOT_DRIVER(stm32_timer) = { 129 .name = "stm32_timer", 130 .id = UCLASS_TIMER, 131 .of_match = stm32_timer_ids, 132 .priv_auto_alloc_size = sizeof(struct stm32_timer_priv), 133 .probe = stm32_timer_probe, 134 .ops = &stm32_timer_ops, 135 }; 136 137