1 /*
2  * Andestech ATCPIT100 timer driver
3  *
4  * (C) Copyright 2016
5  * Rick Chen, NDS32 Software Engineering, rick@andestech.com
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 #include <common.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <timer.h>
13 #include <linux/io.h>
14 
15 #define REG32_TMR(x)	(*(u32 *)	((plat->regs) + (x>>2)))
16 
17 /*
18  * Definition of register offsets
19  */
20 
21 /* ID and Revision Register */
22 #define ID_REV		0x0
23 
24 /* Configuration Register */
25 #define CFG		0x10
26 
27 /* Interrupt Enable Register */
28 #define INT_EN		0x14
29 #define CH_INT_EN(c , i)	((1<<i)<<(4*c))
30 
31 /* Interrupt Status Register */
32 #define INT_STA		0x18
33 #define CH_INT_STA(c , i)	((1<<i)<<(4*c))
34 
35 /* Channel Enable Register */
36 #define CH_EN		0x1C
37 #define CH_TMR_EN(c , t)	((1<<t)<<(4*c))
38 
39 /* Ch n Control REgister */
40 #define CH_CTL(n)	(0x20+0x10*n)
41 /* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
42 #define APB_CLK		(1<<3)
43 /* Channel mode , bit 0~2 */
44 #define TMR_32		1
45 #define TMR_16		2
46 #define TMR_8		3
47 #define PWM		4
48 
49 #define CH_REL(n)	(0x24+0x10*n)
50 #define CH_CNT(n)	(0x28+0x10*n)
51 
52 struct atctmr_timer_regs {
53 	u32	id_rev;		/* 0x00 */
54 	u32	reservd[3];	/* 0x04 ~ 0x0c */
55 	u32	cfg;		/* 0x10 */
56 	u32	int_en;		/* 0x14 */
57 	u32	int_st;		/* 0x18 */
58 	u32	ch_en;		/* 0x1c */
59 	u32	ch0_ctrl;	/* 0x20 */
60 	u32	ch0_reload;	/* 0x24 */
61 	u32	ch0_cntr;	/* 0x28 */
62 	u32	reservd1;	/* 0x2c */
63 	u32	ch1_ctrl;	/* 0x30 */
64 	u32	ch1_reload;	/* 0x34 */
65 	u32	int_mask;	/* 0x38 */
66 };
67 
68 struct atcpit_timer_platdata {
69 	u32 *regs;
70 };
71 
72 static int atcpit_timer_get_count(struct udevice *dev, u64 *count)
73 {
74 	struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
75 	u32 val;
76 	val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
77 	*count = timer_conv_64(val);
78 	return 0;
79 }
80 
81 static int atcpit_timer_probe(struct udevice *dev)
82 {
83 	struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
84 	REG32_TMR(CH_REL(1)) = 0xffffffff;
85 	REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
86 	REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
87 	return 0;
88 }
89 
90 static int atcpit_timer_ofdata_to_platdata(struct udevice *dev)
91 {
92 	struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
93 	plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE);
94 	return 0;
95 }
96 
97 static const struct timer_ops atcpit_timer_ops = {
98 	.get_count = atcpit_timer_get_count,
99 };
100 
101 static const struct udevice_id atcpit_timer_ids[] = {
102 	{ .compatible = "andestech,atcpit100" },
103 	{}
104 };
105 
106 U_BOOT_DRIVER(atcpit100_timer) = {
107 	.name	= "atcpit100_timer",
108 	.id	= UCLASS_TIMER,
109 	.of_match = atcpit_timer_ids,
110 	.ofdata_to_platdata = atcpit_timer_ofdata_to_platdata,
111 	.platdata_auto_alloc_size = sizeof(struct atcpit_timer_platdata),
112 	.probe = atcpit_timer_probe,
113 	.ops	= &atcpit_timer_ops,
114 	.flags = DM_FLAG_PRE_RELOC,
115 };
116