1 /* 2 * (C) Copyright 2000-2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2004, Psyent Corporation <www.psyent.com> 6 * Scott McNutt <smcnutt@psyent.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <errno.h> 14 #include <timer.h> 15 #include <asm/io.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 /* control register */ 20 #define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */ 21 #define ALTERA_TIMER_START BIT(2) /* Start timer */ 22 #define ALTERA_TIMER_STOP BIT(3) /* Stop timer */ 23 24 struct altera_timer_regs { 25 u32 status; /* Timer status reg */ 26 u32 control; /* Timer control reg */ 27 u32 periodl; /* Timeout period low */ 28 u32 periodh; /* Timeout period high */ 29 u32 snapl; /* Snapshot low */ 30 u32 snaph; /* Snapshot high */ 31 }; 32 33 struct altera_timer_platdata { 34 struct altera_timer_regs *regs; 35 unsigned long clock_rate; 36 }; 37 38 static int altera_timer_get_count(struct udevice *dev, unsigned long *count) 39 { 40 struct altera_timer_platdata *plat = dev->platdata; 41 struct altera_timer_regs *const regs = plat->regs; 42 u32 val; 43 44 /* Trigger update */ 45 writel(0x0, ®s->snapl); 46 47 /* Read timer value */ 48 val = readl(®s->snapl) & 0xffff; 49 val |= (readl(®s->snaph) & 0xffff) << 16; 50 *count = ~val; 51 52 return 0; 53 } 54 55 static int altera_timer_probe(struct udevice *dev) 56 { 57 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); 58 struct altera_timer_platdata *plat = dev->platdata; 59 struct altera_timer_regs *const regs = plat->regs; 60 61 uc_priv->clock_rate = plat->clock_rate; 62 63 writel(0, ®s->status); 64 writel(0, ®s->control); 65 writel(ALTERA_TIMER_STOP, ®s->control); 66 67 writel(0xffff, ®s->periodl); 68 writel(0xffff, ®s->periodh); 69 writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, ®s->control); 70 71 return 0; 72 } 73 74 static int altera_timer_ofdata_to_platdata(struct udevice *dev) 75 { 76 struct altera_timer_platdata *plat = dev_get_platdata(dev); 77 78 plat->regs = map_physmem(dev_get_addr(dev), 79 sizeof(struct altera_timer_regs), 80 MAP_NOCACHE); 81 plat->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset, 82 "clock-frequency", 0); 83 84 return 0; 85 } 86 87 static const struct timer_ops altera_timer_ops = { 88 .get_count = altera_timer_get_count, 89 }; 90 91 static const struct udevice_id altera_timer_ids[] = { 92 { .compatible = "altr,timer-1.0" }, 93 {} 94 }; 95 96 U_BOOT_DRIVER(altera_timer) = { 97 .name = "altera_timer", 98 .id = UCLASS_TIMER, 99 .of_match = altera_timer_ids, 100 .ofdata_to_platdata = altera_timer_ofdata_to_platdata, 101 .platdata_auto_alloc_size = sizeof(struct altera_timer_platdata), 102 .probe = altera_timer_probe, 103 .ops = &altera_timer_ops, 104 .flags = DM_FLAG_PRE_RELOC, 105 }; 106