1 /* 2 * Andestech ATFTMR010 timer driver 3 * 4 * (C) Copyright 2016 5 * Rick Chen, NDS32 Software Engineering, rick@andestech.com 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #include <common.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <timer.h> 13 #include <linux/io.h> 14 15 /* 16 * Timer Control Register 17 */ 18 #define T3_UPDOWN (1 << 11) 19 #define T2_UPDOWN (1 << 10) 20 #define T1_UPDOWN (1 << 9) 21 #define T3_OFENABLE (1 << 8) 22 #define T3_CLOCK (1 << 7) 23 #define T3_ENABLE (1 << 6) 24 #define T2_OFENABLE (1 << 5) 25 #define T2_CLOCK (1 << 4) 26 #define T2_ENABLE (1 << 3) 27 #define T1_OFENABLE (1 << 2) 28 #define T1_CLOCK (1 << 1) 29 #define T1_ENABLE (1 << 0) 30 31 /* 32 * Timer Interrupt State & Mask Registers 33 */ 34 #define T3_OVERFLOW (1 << 8) 35 #define T3_MATCH2 (1 << 7) 36 #define T3_MATCH1 (1 << 6) 37 #define T2_OVERFLOW (1 << 5) 38 #define T2_MATCH2 (1 << 4) 39 #define T2_MATCH1 (1 << 3) 40 #define T1_OVERFLOW (1 << 2) 41 #define T1_MATCH2 (1 << 1) 42 #define T1_MATCH1 (1 << 0) 43 44 struct atftmr_timer_regs { 45 u32 t1_counter; /* 0x00 */ 46 u32 t1_load; /* 0x04 */ 47 u32 t1_match1; /* 0x08 */ 48 u32 t1_match2; /* 0x0c */ 49 u32 t2_counter; /* 0x10 */ 50 u32 t2_load; /* 0x14 */ 51 u32 t2_match1; /* 0x18 */ 52 u32 t2_match2; /* 0x1c */ 53 u32 t3_counter; /* 0x20 */ 54 u32 t3_load; /* 0x24 */ 55 u32 t3_match1; /* 0x28 */ 56 u32 t3_match2; /* 0x2c */ 57 u32 cr; /* 0x30 */ 58 u32 int_state; /* 0x34 */ 59 u32 int_mask; /* 0x38 */ 60 }; 61 62 struct atftmr_timer_platdata { 63 struct atftmr_timer_regs *regs; 64 }; 65 66 static int atftmr_timer_get_count(struct udevice *dev, u64 *count) 67 { 68 struct atftmr_timer_platdata *plat = dev->platdata; 69 struct atftmr_timer_regs *const regs = plat->regs; 70 u32 val; 71 val = readl(®s->t3_counter); 72 *count = timer_conv_64(val); 73 return 0; 74 } 75 76 static int atftmr_timer_probe(struct udevice *dev) 77 { 78 struct atftmr_timer_platdata *plat = dev->platdata; 79 struct atftmr_timer_regs *const regs = plat->regs; 80 u32 cr; 81 writel(0, ®s->t3_load); 82 writel(0, ®s->t3_counter); 83 writel(TIMER_LOAD_VAL, ®s->t3_match1); 84 writel(TIMER_LOAD_VAL, ®s->t3_match2); 85 /* disable interrupts */ 86 writel(T3_MATCH1|T3_MATCH2|T3_OVERFLOW , ®s->int_mask); 87 cr = readl(®s->cr); 88 cr |= (T3_ENABLE|T3_UPDOWN); 89 writel(cr, ®s->cr); 90 return 0; 91 } 92 93 static int atftme_timer_ofdata_to_platdata(struct udevice *dev) 94 { 95 struct atftmr_timer_platdata *plat = dev_get_platdata(dev); 96 plat->regs = map_physmem(devfdt_get_addr(dev), 97 sizeof(struct atftmr_timer_regs), 98 MAP_NOCACHE); 99 return 0; 100 } 101 102 static const struct timer_ops ag101p_timer_ops = { 103 .get_count = atftmr_timer_get_count, 104 }; 105 106 static const struct udevice_id ag101p_timer_ids[] = { 107 { .compatible = "andestech,attmr010" }, 108 {} 109 }; 110 111 U_BOOT_DRIVER(altera_timer) = { 112 .name = "ag101p_timer", 113 .id = UCLASS_TIMER, 114 .of_match = ag101p_timer_ids, 115 .ofdata_to_platdata = atftme_timer_ofdata_to_platdata, 116 .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata), 117 .probe = atftmr_timer_probe, 118 .ops = &ag101p_timer_ops, 119 .flags = DM_FLAG_PRE_RELOC, 120 }; 121