1 /* 2 * (C) Copyright 2013 Inc. 3 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com> 4 * 5 * Xilinx Zynq PS SPI controller driver (master mode only) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <dm.h> 13 #include <errno.h> 14 #include <malloc.h> 15 #include <spi.h> 16 #include <asm/io.h> 17 #include <asm/arch/hardware.h> 18 19 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */ 20 #define ZYNQ_SPI_CR_MSA_MASK (1 << 15) /* Manual start enb */ 21 #define ZYNQ_SPI_CR_MCS_MASK (1 << 14) /* Manual chip select */ 22 #define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */ 23 #define ZYNQ_SPI_CR_BRD_MASK (0x7 << 3) /* Baud rate div */ 24 #define ZYNQ_SPI_CR_CPHA_MASK (1 << 2) /* Clock phase */ 25 #define ZYNQ_SPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */ 26 #define ZYNQ_SPI_CR_MSTREN_MASK (1 << 0) /* Mode select */ 27 #define ZYNQ_SPI_IXR_RXNEMPTY_MASK (1 << 4) /* RX_FIFO_not_empty */ 28 #define ZYNQ_SPI_IXR_TXOW_MASK (1 << 2) /* TX_FIFO_not_full */ 29 #define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ 30 #define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */ 31 32 #define ZYNQ_SPI_FIFO_DEPTH 128 33 #ifndef CONFIG_SYS_ZYNQ_SPI_WAIT 34 #define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ 35 #endif 36 37 /* zynq spi register set */ 38 struct zynq_spi_regs { 39 u32 cr; /* 0x00 */ 40 u32 isr; /* 0x04 */ 41 u32 ier; /* 0x08 */ 42 u32 idr; /* 0x0C */ 43 u32 imr; /* 0x10 */ 44 u32 enr; /* 0x14 */ 45 u32 dr; /* 0x18 */ 46 u32 txdr; /* 0x1C */ 47 u32 rxdr; /* 0x20 */ 48 }; 49 50 51 /* zynq spi platform data */ 52 struct zynq_spi_platdata { 53 struct zynq_spi_regs *regs; 54 u32 frequency; /* input frequency */ 55 u32 speed_hz; 56 }; 57 58 /* zynq spi priv */ 59 struct zynq_spi_priv { 60 struct zynq_spi_regs *regs; 61 u8 mode; 62 u8 fifo_depth; 63 u32 freq; /* required frequency */ 64 }; 65 66 static inline struct zynq_spi_regs *get_zynq_spi_regs(struct udevice *bus) 67 { 68 if (bus->seq) 69 return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1; 70 else 71 return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0; 72 } 73 74 static int zynq_spi_ofdata_to_platdata(struct udevice *bus) 75 { 76 struct zynq_spi_platdata *plat = bus->platdata; 77 78 plat->regs = get_zynq_spi_regs(bus); 79 plat->frequency = 166666700; 80 plat->speed_hz = plat->frequency / 2; 81 82 return 0; 83 } 84 85 static void zynq_spi_init_hw(struct zynq_spi_priv *priv) 86 { 87 struct zynq_spi_regs *regs = priv->regs; 88 u32 confr; 89 90 /* Disable SPI */ 91 writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); 92 93 /* Disable Interrupts */ 94 writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->idr); 95 96 /* Clear RX FIFO */ 97 while (readl(®s->isr) & 98 ZYNQ_SPI_IXR_RXNEMPTY_MASK) 99 readl(®s->rxdr); 100 101 /* Clear Interrupts */ 102 writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->isr); 103 104 /* Manual slave select and Auto start */ 105 confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK | 106 ZYNQ_SPI_CR_MSTREN_MASK; 107 confr &= ~ZYNQ_SPI_CR_MSA_MASK; 108 writel(confr, ®s->cr); 109 110 /* Enable SPI */ 111 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); 112 } 113 114 static int zynq_spi_probe(struct udevice *bus) 115 { 116 struct zynq_spi_platdata *plat = dev_get_platdata(bus); 117 struct zynq_spi_priv *priv = dev_get_priv(bus); 118 119 priv->regs = plat->regs; 120 priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH; 121 122 /* init the zynq spi hw */ 123 zynq_spi_init_hw(priv); 124 125 return 0; 126 } 127 128 static void spi_cs_activate(struct udevice *dev, uint cs) 129 { 130 struct udevice *bus = dev->parent; 131 struct zynq_spi_priv *priv = dev_get_priv(bus); 132 struct zynq_spi_regs *regs = priv->regs; 133 u32 cr; 134 135 clrbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK); 136 cr = readl(®s->cr); 137 /* 138 * CS cal logic: CS[13:10] 139 * xxx0 - cs0 140 * xx01 - cs1 141 * x011 - cs2 142 */ 143 cr |= (~(0x1 << cs) << 10) & ZYNQ_SPI_CR_CS_MASK; 144 writel(cr, ®s->cr); 145 } 146 147 static void spi_cs_deactivate(struct udevice *dev) 148 { 149 struct udevice *bus = dev->parent; 150 struct zynq_spi_priv *priv = dev_get_priv(bus); 151 struct zynq_spi_regs *regs = priv->regs; 152 153 setbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK); 154 } 155 156 static int zynq_spi_claim_bus(struct udevice *dev) 157 { 158 struct udevice *bus = dev->parent; 159 struct zynq_spi_priv *priv = dev_get_priv(bus); 160 struct zynq_spi_regs *regs = priv->regs; 161 162 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); 163 164 return 0; 165 } 166 167 static int zynq_spi_release_bus(struct udevice *dev) 168 { 169 struct udevice *bus = dev->parent; 170 struct zynq_spi_priv *priv = dev_get_priv(bus); 171 struct zynq_spi_regs *regs = priv->regs; 172 173 writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); 174 175 return 0; 176 } 177 178 static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen, 179 const void *dout, void *din, unsigned long flags) 180 { 181 struct udevice *bus = dev->parent; 182 struct zynq_spi_priv *priv = dev_get_priv(bus); 183 struct zynq_spi_regs *regs = priv->regs; 184 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 185 u32 len = bitlen / 8; 186 u32 tx_len = len, rx_len = len, tx_tvl; 187 const u8 *tx_buf = dout; 188 u8 *rx_buf = din, buf; 189 u32 ts, status; 190 191 debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", 192 bus->seq, slave_plat->cs, bitlen, len, flags); 193 194 if (bitlen % 8) { 195 debug("spi_xfer: Non byte aligned SPI transfer\n"); 196 return -1; 197 } 198 199 if (flags & SPI_XFER_BEGIN) 200 spi_cs_activate(dev, slave_plat->cs); 201 202 while (rx_len > 0) { 203 /* Write the data into TX FIFO - tx threshold is fifo_depth */ 204 tx_tvl = 0; 205 while ((tx_tvl < priv->fifo_depth) && tx_len) { 206 if (tx_buf) 207 buf = *tx_buf++; 208 else 209 buf = 0; 210 writel(buf, ®s->txdr); 211 tx_len--; 212 tx_tvl++; 213 } 214 215 /* Check TX FIFO completion */ 216 ts = get_timer(0); 217 status = readl(®s->isr); 218 while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) { 219 if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) { 220 printf("spi_xfer: Timeout! TX FIFO not full\n"); 221 return -1; 222 } 223 status = readl(®s->isr); 224 } 225 226 /* Read the data from RX FIFO */ 227 status = readl(®s->isr); 228 while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) { 229 buf = readl(®s->rxdr); 230 if (rx_buf) 231 *rx_buf++ = buf; 232 status = readl(®s->isr); 233 rx_len--; 234 } 235 } 236 237 if (flags & SPI_XFER_END) 238 spi_cs_deactivate(dev); 239 240 return 0; 241 } 242 243 static int zynq_spi_set_speed(struct udevice *bus, uint speed) 244 { 245 struct zynq_spi_platdata *plat = bus->platdata; 246 struct zynq_spi_priv *priv = dev_get_priv(bus); 247 struct zynq_spi_regs *regs = priv->regs; 248 uint32_t confr; 249 u8 baud_rate_val = 0; 250 251 if (speed > plat->frequency) 252 speed = plat->frequency; 253 254 /* Set the clock frequency */ 255 confr = readl(®s->cr); 256 if (speed == 0) { 257 /* Set baudrate x8, if the freq is 0 */ 258 baud_rate_val = 0x2; 259 } else if (plat->speed_hz != speed) { 260 while ((baud_rate_val < 8) && 261 ((plat->frequency / 262 (2 << baud_rate_val)) > speed)) 263 baud_rate_val++; 264 plat->speed_hz = speed / (2 << baud_rate_val); 265 } 266 confr &= ~ZYNQ_SPI_CR_BRD_MASK; 267 confr |= (baud_rate_val << 3); 268 269 writel(confr, ®s->cr); 270 priv->freq = speed; 271 272 debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq); 273 274 return 0; 275 } 276 277 static int zynq_spi_set_mode(struct udevice *bus, uint mode) 278 { 279 struct zynq_spi_priv *priv = dev_get_priv(bus); 280 struct zynq_spi_regs *regs = priv->regs; 281 uint32_t confr; 282 283 /* Set the SPI Clock phase and polarities */ 284 confr = readl(®s->cr); 285 confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK); 286 287 if (priv->mode & SPI_CPHA) 288 confr |= ZYNQ_SPI_CR_CPHA_MASK; 289 if (priv->mode & SPI_CPOL) 290 confr |= ZYNQ_SPI_CR_CPOL_MASK; 291 292 writel(confr, ®s->cr); 293 priv->mode = mode; 294 295 debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode); 296 297 return 0; 298 } 299 300 static const struct dm_spi_ops zynq_spi_ops = { 301 .claim_bus = zynq_spi_claim_bus, 302 .release_bus = zynq_spi_release_bus, 303 .xfer = zynq_spi_xfer, 304 .set_speed = zynq_spi_set_speed, 305 .set_mode = zynq_spi_set_mode, 306 }; 307 308 static const struct udevice_id zynq_spi_ids[] = { 309 { .compatible = "xlnx,zynq-spi" }, 310 { } 311 }; 312 313 U_BOOT_DRIVER(zynq_spi) = { 314 .name = "zynq_spi", 315 .id = UCLASS_SPI, 316 .of_match = zynq_spi_ids, 317 .ops = &zynq_spi_ops, 318 .ofdata_to_platdata = zynq_spi_ofdata_to_platdata, 319 .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata), 320 .priv_auto_alloc_size = sizeof(struct zynq_spi_priv), 321 .probe = zynq_spi_probe, 322 }; 323