1 /* 2 * (C) Copyright 2013 Inc. 3 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com> 4 * 5 * Xilinx Zynq PS SPI controller driver (master mode only) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <dm.h> 13 #include <errno.h> 14 #include <malloc.h> 15 #include <spi.h> 16 #include <fdtdec.h> 17 #include <asm/io.h> 18 #include <asm/arch/hardware.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */ 23 #define ZYNQ_SPI_CR_MSA_MASK (1 << 15) /* Manual start enb */ 24 #define ZYNQ_SPI_CR_MCS_MASK (1 << 14) /* Manual chip select */ 25 #define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */ 26 #define ZYNQ_SPI_CR_BRD_MASK (0x7 << 3) /* Baud rate div */ 27 #define ZYNQ_SPI_CR_CPHA_MASK (1 << 2) /* Clock phase */ 28 #define ZYNQ_SPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */ 29 #define ZYNQ_SPI_CR_MSTREN_MASK (1 << 0) /* Mode select */ 30 #define ZYNQ_SPI_IXR_RXNEMPTY_MASK (1 << 4) /* RX_FIFO_not_empty */ 31 #define ZYNQ_SPI_IXR_TXOW_MASK (1 << 2) /* TX_FIFO_not_full */ 32 #define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ 33 #define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */ 34 35 #define ZYNQ_SPI_FIFO_DEPTH 128 36 #ifndef CONFIG_SYS_ZYNQ_SPI_WAIT 37 #define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ 38 #endif 39 40 /* zynq spi register set */ 41 struct zynq_spi_regs { 42 u32 cr; /* 0x00 */ 43 u32 isr; /* 0x04 */ 44 u32 ier; /* 0x08 */ 45 u32 idr; /* 0x0C */ 46 u32 imr; /* 0x10 */ 47 u32 enr; /* 0x14 */ 48 u32 dr; /* 0x18 */ 49 u32 txdr; /* 0x1C */ 50 u32 rxdr; /* 0x20 */ 51 }; 52 53 54 /* zynq spi platform data */ 55 struct zynq_spi_platdata { 56 struct zynq_spi_regs *regs; 57 u32 frequency; /* input frequency */ 58 u32 speed_hz; 59 }; 60 61 /* zynq spi priv */ 62 struct zynq_spi_priv { 63 struct zynq_spi_regs *regs; 64 u8 mode; 65 u8 fifo_depth; 66 u32 freq; /* required frequency */ 67 }; 68 69 static int zynq_spi_ofdata_to_platdata(struct udevice *bus) 70 { 71 struct zynq_spi_platdata *plat = bus->platdata; 72 const void *blob = gd->fdt_blob; 73 int node = bus->of_offset; 74 75 plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus); 76 77 /* FIXME: Use 250MHz as a suitable default */ 78 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 79 250000000); 80 plat->speed_hz = plat->frequency / 2; 81 82 debug("%s: regs=%p max-frequency=%d\n", __func__, 83 plat->regs, plat->frequency); 84 85 return 0; 86 } 87 88 static void zynq_spi_init_hw(struct zynq_spi_priv *priv) 89 { 90 struct zynq_spi_regs *regs = priv->regs; 91 u32 confr; 92 93 /* Disable SPI */ 94 writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); 95 96 /* Disable Interrupts */ 97 writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->idr); 98 99 /* Clear RX FIFO */ 100 while (readl(®s->isr) & 101 ZYNQ_SPI_IXR_RXNEMPTY_MASK) 102 readl(®s->rxdr); 103 104 /* Clear Interrupts */ 105 writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->isr); 106 107 /* Manual slave select and Auto start */ 108 confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK | 109 ZYNQ_SPI_CR_MSTREN_MASK; 110 confr &= ~ZYNQ_SPI_CR_MSA_MASK; 111 writel(confr, ®s->cr); 112 113 /* Enable SPI */ 114 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); 115 } 116 117 static int zynq_spi_probe(struct udevice *bus) 118 { 119 struct zynq_spi_platdata *plat = dev_get_platdata(bus); 120 struct zynq_spi_priv *priv = dev_get_priv(bus); 121 122 priv->regs = plat->regs; 123 priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH; 124 125 /* init the zynq spi hw */ 126 zynq_spi_init_hw(priv); 127 128 return 0; 129 } 130 131 static void spi_cs_activate(struct udevice *dev, uint cs) 132 { 133 struct udevice *bus = dev->parent; 134 struct zynq_spi_priv *priv = dev_get_priv(bus); 135 struct zynq_spi_regs *regs = priv->regs; 136 u32 cr; 137 138 clrbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK); 139 cr = readl(®s->cr); 140 /* 141 * CS cal logic: CS[13:10] 142 * xxx0 - cs0 143 * xx01 - cs1 144 * x011 - cs2 145 */ 146 cr |= (~(0x1 << cs) << 10) & ZYNQ_SPI_CR_CS_MASK; 147 writel(cr, ®s->cr); 148 } 149 150 static void spi_cs_deactivate(struct udevice *dev) 151 { 152 struct udevice *bus = dev->parent; 153 struct zynq_spi_priv *priv = dev_get_priv(bus); 154 struct zynq_spi_regs *regs = priv->regs; 155 156 setbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK); 157 } 158 159 static int zynq_spi_claim_bus(struct udevice *dev) 160 { 161 struct udevice *bus = dev->parent; 162 struct zynq_spi_priv *priv = dev_get_priv(bus); 163 struct zynq_spi_regs *regs = priv->regs; 164 165 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); 166 167 return 0; 168 } 169 170 static int zynq_spi_release_bus(struct udevice *dev) 171 { 172 struct udevice *bus = dev->parent; 173 struct zynq_spi_priv *priv = dev_get_priv(bus); 174 struct zynq_spi_regs *regs = priv->regs; 175 176 writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); 177 178 return 0; 179 } 180 181 static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen, 182 const void *dout, void *din, unsigned long flags) 183 { 184 struct udevice *bus = dev->parent; 185 struct zynq_spi_priv *priv = dev_get_priv(bus); 186 struct zynq_spi_regs *regs = priv->regs; 187 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 188 u32 len = bitlen / 8; 189 u32 tx_len = len, rx_len = len, tx_tvl; 190 const u8 *tx_buf = dout; 191 u8 *rx_buf = din, buf; 192 u32 ts, status; 193 194 debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", 195 bus->seq, slave_plat->cs, bitlen, len, flags); 196 197 if (bitlen % 8) { 198 debug("spi_xfer: Non byte aligned SPI transfer\n"); 199 return -1; 200 } 201 202 if (flags & SPI_XFER_BEGIN) 203 spi_cs_activate(dev, slave_plat->cs); 204 205 while (rx_len > 0) { 206 /* Write the data into TX FIFO - tx threshold is fifo_depth */ 207 tx_tvl = 0; 208 while ((tx_tvl < priv->fifo_depth) && tx_len) { 209 if (tx_buf) 210 buf = *tx_buf++; 211 else 212 buf = 0; 213 writel(buf, ®s->txdr); 214 tx_len--; 215 tx_tvl++; 216 } 217 218 /* Check TX FIFO completion */ 219 ts = get_timer(0); 220 status = readl(®s->isr); 221 while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) { 222 if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) { 223 printf("spi_xfer: Timeout! TX FIFO not full\n"); 224 return -1; 225 } 226 status = readl(®s->isr); 227 } 228 229 /* Read the data from RX FIFO */ 230 status = readl(®s->isr); 231 while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) { 232 buf = readl(®s->rxdr); 233 if (rx_buf) 234 *rx_buf++ = buf; 235 status = readl(®s->isr); 236 rx_len--; 237 } 238 } 239 240 if (flags & SPI_XFER_END) 241 spi_cs_deactivate(dev); 242 243 return 0; 244 } 245 246 static int zynq_spi_set_speed(struct udevice *bus, uint speed) 247 { 248 struct zynq_spi_platdata *plat = bus->platdata; 249 struct zynq_spi_priv *priv = dev_get_priv(bus); 250 struct zynq_spi_regs *regs = priv->regs; 251 uint32_t confr; 252 u8 baud_rate_val = 0; 253 254 if (speed > plat->frequency) 255 speed = plat->frequency; 256 257 /* Set the clock frequency */ 258 confr = readl(®s->cr); 259 if (speed == 0) { 260 /* Set baudrate x8, if the freq is 0 */ 261 baud_rate_val = 0x2; 262 } else if (plat->speed_hz != speed) { 263 while ((baud_rate_val < 8) && 264 ((plat->frequency / 265 (2 << baud_rate_val)) > speed)) 266 baud_rate_val++; 267 plat->speed_hz = speed / (2 << baud_rate_val); 268 } 269 confr &= ~ZYNQ_SPI_CR_BRD_MASK; 270 confr |= (baud_rate_val << 3); 271 272 writel(confr, ®s->cr); 273 priv->freq = speed; 274 275 debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq); 276 277 return 0; 278 } 279 280 static int zynq_spi_set_mode(struct udevice *bus, uint mode) 281 { 282 struct zynq_spi_priv *priv = dev_get_priv(bus); 283 struct zynq_spi_regs *regs = priv->regs; 284 uint32_t confr; 285 286 /* Set the SPI Clock phase and polarities */ 287 confr = readl(®s->cr); 288 confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK); 289 290 if (priv->mode & SPI_CPHA) 291 confr |= ZYNQ_SPI_CR_CPHA_MASK; 292 if (priv->mode & SPI_CPOL) 293 confr |= ZYNQ_SPI_CR_CPOL_MASK; 294 295 writel(confr, ®s->cr); 296 priv->mode = mode; 297 298 debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode); 299 300 return 0; 301 } 302 303 static const struct dm_spi_ops zynq_spi_ops = { 304 .claim_bus = zynq_spi_claim_bus, 305 .release_bus = zynq_spi_release_bus, 306 .xfer = zynq_spi_xfer, 307 .set_speed = zynq_spi_set_speed, 308 .set_mode = zynq_spi_set_mode, 309 }; 310 311 static const struct udevice_id zynq_spi_ids[] = { 312 { .compatible = "xlnx,zynq-spi-r1p6" }, 313 { } 314 }; 315 316 U_BOOT_DRIVER(zynq_spi) = { 317 .name = "zynq_spi", 318 .id = UCLASS_SPI, 319 .of_match = zynq_spi_ids, 320 .ops = &zynq_spi_ops, 321 .ofdata_to_platdata = zynq_spi_ofdata_to_platdata, 322 .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata), 323 .priv_auto_alloc_size = sizeof(struct zynq_spi_priv), 324 .probe = zynq_spi_probe, 325 }; 326