1 /* 2 * (C) Copyright 2013 Xilinx, Inc. 3 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com> 4 * 5 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <malloc.h> 13 #include <spi.h> 14 #include <asm/io.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */ 19 #define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/ 20 #define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */ 21 #define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */ 22 #define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */ 23 #define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */ 24 #define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */ 25 #define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */ 26 #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */ 27 #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ 28 #define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */ 29 #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ 30 #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ 31 #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ 32 #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ 33 34 /* zynq qspi Transmit Data Register */ 35 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */ 36 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */ 37 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */ 38 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */ 39 40 #define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/ 41 #define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */ 42 43 #define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */ 44 #define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */ 45 #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */ 46 47 #define ZYNQ_QSPI_FIFO_DEPTH 63 48 #ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT 49 #define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ 50 #endif 51 52 /* zynq qspi register set */ 53 struct zynq_qspi_regs { 54 u32 cr; /* 0x00 */ 55 u32 isr; /* 0x04 */ 56 u32 ier; /* 0x08 */ 57 u32 idr; /* 0x0C */ 58 u32 imr; /* 0x10 */ 59 u32 enr; /* 0x14 */ 60 u32 dr; /* 0x18 */ 61 u32 txd0r; /* 0x1C */ 62 u32 drxr; /* 0x20 */ 63 u32 sicr; /* 0x24 */ 64 u32 txftr; /* 0x28 */ 65 u32 rxftr; /* 0x2C */ 66 u32 gpior; /* 0x30 */ 67 u32 reserved0[19]; 68 u32 txd1r; /* 0x80 */ 69 u32 txd2r; /* 0x84 */ 70 u32 txd3r; /* 0x88 */ 71 }; 72 73 /* zynq qspi platform data */ 74 struct zynq_qspi_platdata { 75 struct zynq_qspi_regs *regs; 76 u32 frequency; /* input frequency */ 77 u32 speed_hz; 78 }; 79 80 /* zynq qspi priv */ 81 struct zynq_qspi_priv { 82 struct zynq_qspi_regs *regs; 83 u8 cs; 84 u8 mode; 85 u8 fifo_depth; 86 u32 freq; /* required frequency */ 87 const void *tx_buf; 88 void *rx_buf; 89 unsigned len; 90 int bytes_to_transfer; 91 int bytes_to_receive; 92 unsigned int is_inst; 93 unsigned cs_change:1; 94 }; 95 96 static int zynq_qspi_ofdata_to_platdata(struct udevice *bus) 97 { 98 struct zynq_qspi_platdata *plat = bus->platdata; 99 const void *blob = gd->fdt_blob; 100 int node = bus->of_offset; 101 102 plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob, 103 node, "reg"); 104 105 /* FIXME: Use 166MHz as a suitable default */ 106 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 107 166666666); 108 plat->speed_hz = plat->frequency / 2; 109 110 debug("%s: regs=%p max-frequency=%d\n", __func__, 111 plat->regs, plat->frequency); 112 113 return 0; 114 } 115 116 static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) 117 { 118 struct zynq_qspi_regs *regs = priv->regs; 119 u32 confr; 120 121 /* Disable QSPI */ 122 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); 123 124 /* Disable Interrupts */ 125 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr); 126 127 /* Clear the TX and RX threshold reg */ 128 writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr); 129 writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr); 130 131 /* Clear the RX FIFO */ 132 while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK) 133 readl(®s->drxr); 134 135 /* Clear Interrupts */ 136 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->isr); 137 138 /* Manual slave select and Auto start */ 139 confr = readl(®s->cr); 140 confr &= ~ZYNQ_QSPI_CR_MSA_MASK; 141 confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK | 142 ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK | 143 ZYNQ_QSPI_CR_MSTREN_MASK; 144 writel(confr, ®s->cr); 145 146 /* Enable SPI */ 147 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); 148 } 149 150 static int zynq_qspi_probe(struct udevice *bus) 151 { 152 struct zynq_qspi_platdata *plat = dev_get_platdata(bus); 153 struct zynq_qspi_priv *priv = dev_get_priv(bus); 154 155 priv->regs = plat->regs; 156 priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH; 157 158 /* init the zynq spi hw */ 159 zynq_qspi_init_hw(priv); 160 161 return 0; 162 } 163 164 /* 165 * zynq_qspi_read_data - Copy data to RX buffer 166 * @zqspi: Pointer to the zynq_qspi structure 167 * @data: The 32 bit variable where data is stored 168 * @size: Number of bytes to be copied from data to RX buffer 169 */ 170 static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size) 171 { 172 u8 byte3; 173 174 debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ , 175 data, (unsigned)(priv->rx_buf), size); 176 177 if (priv->rx_buf) { 178 switch (size) { 179 case 1: 180 *((u8 *)priv->rx_buf) = data; 181 priv->rx_buf += 1; 182 break; 183 case 2: 184 *((u16 *)priv->rx_buf) = data; 185 priv->rx_buf += 2; 186 break; 187 case 3: 188 *((u16 *)priv->rx_buf) = data; 189 priv->rx_buf += 2; 190 byte3 = (u8)(data >> 16); 191 *((u8 *)priv->rx_buf) = byte3; 192 priv->rx_buf += 1; 193 break; 194 case 4: 195 /* Can not assume word aligned buffer */ 196 memcpy(priv->rx_buf, &data, size); 197 priv->rx_buf += 4; 198 break; 199 default: 200 /* This will never execute */ 201 break; 202 } 203 } 204 priv->bytes_to_receive -= size; 205 if (priv->bytes_to_receive < 0) 206 priv->bytes_to_receive = 0; 207 } 208 209 /* 210 * zynq_qspi_write_data - Copy data from TX buffer 211 * @zqspi: Pointer to the zynq_qspi structure 212 * @data: Pointer to the 32 bit variable where data is to be copied 213 * @size: Number of bytes to be copied from TX buffer to data 214 */ 215 static void zynq_qspi_write_data(struct zynq_qspi_priv *priv, 216 u32 *data, u8 size) 217 { 218 if (priv->tx_buf) { 219 switch (size) { 220 case 1: 221 *data = *((u8 *)priv->tx_buf); 222 priv->tx_buf += 1; 223 *data |= 0xFFFFFF00; 224 break; 225 case 2: 226 *data = *((u16 *)priv->tx_buf); 227 priv->tx_buf += 2; 228 *data |= 0xFFFF0000; 229 break; 230 case 3: 231 *data = *((u16 *)priv->tx_buf); 232 priv->tx_buf += 2; 233 *data |= (*((u8 *)priv->tx_buf) << 16); 234 priv->tx_buf += 1; 235 *data |= 0xFF000000; 236 break; 237 case 4: 238 /* Can not assume word aligned buffer */ 239 memcpy(data, priv->tx_buf, size); 240 priv->tx_buf += 4; 241 break; 242 default: 243 /* This will never execute */ 244 break; 245 } 246 } else { 247 *data = 0; 248 } 249 250 debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__, 251 *data, (u32)priv->tx_buf, size); 252 253 priv->bytes_to_transfer -= size; 254 if (priv->bytes_to_transfer < 0) 255 priv->bytes_to_transfer = 0; 256 } 257 258 static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on) 259 { 260 u32 confr; 261 struct zynq_qspi_regs *regs = priv->regs; 262 263 confr = readl(®s->cr); 264 265 if (is_on) { 266 /* Select the slave */ 267 confr &= ~ZYNQ_QSPI_CR_SS_MASK; 268 confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) & 269 ZYNQ_QSPI_CR_SS_MASK; 270 } else 271 /* Deselect the slave */ 272 confr |= ZYNQ_QSPI_CR_SS_MASK; 273 274 writel(confr, ®s->cr); 275 } 276 277 /* 278 * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible 279 * @zqspi: Pointer to the zynq_qspi structure 280 */ 281 static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size) 282 { 283 u32 data = 0; 284 u32 fifocount = 0; 285 unsigned len, offset; 286 struct zynq_qspi_regs *regs = priv->regs; 287 static const unsigned offsets[4] = { 288 ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET, 289 ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET }; 290 291 while ((fifocount < size) && 292 (priv->bytes_to_transfer > 0)) { 293 if (priv->bytes_to_transfer >= 4) { 294 if (priv->tx_buf) { 295 memcpy(&data, priv->tx_buf, 4); 296 priv->tx_buf += 4; 297 } else { 298 data = 0; 299 } 300 writel(data, ®s->txd0r); 301 priv->bytes_to_transfer -= 4; 302 fifocount++; 303 } else { 304 /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */ 305 if (!(readl(®s->isr) 306 & ZYNQ_QSPI_IXR_TXOW_MASK) && 307 !priv->rx_buf) 308 return; 309 len = priv->bytes_to_transfer; 310 zynq_qspi_write_data(priv, &data, len); 311 offset = (priv->rx_buf) ? offsets[0] : offsets[len]; 312 writel(data, ®s->cr + (offset / 4)); 313 } 314 } 315 } 316 317 /* 318 * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller 319 * @zqspi: Pointer to the zynq_qspi structure 320 * 321 * This function handles TX empty and Mode Fault interrupts only. 322 * On TX empty interrupt this function reads the received data from RX FIFO and 323 * fills the TX FIFO if there is any data remaining to be transferred. 324 * On Mode Fault interrupt this function indicates that transfer is completed, 325 * the SPI subsystem will identify the error as the remaining bytes to be 326 * transferred is non-zero. 327 * 328 * returns: 0 for poll timeout 329 * 1 transfer operation complete 330 */ 331 static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv) 332 { 333 struct zynq_qspi_regs *regs = priv->regs; 334 u32 rxindex = 0; 335 u32 rxcount; 336 u32 status, timeout; 337 338 /* Poll until any of the interrupt status bits are set */ 339 timeout = get_timer(0); 340 do { 341 status = readl(®s->isr); 342 } while ((status == 0) && 343 (get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT)); 344 345 if (status == 0) { 346 printf("zynq_qspi_irq_poll: Timeout!\n"); 347 return -ETIMEDOUT; 348 } 349 350 writel(status, ®s->isr); 351 352 /* Disable all interrupts */ 353 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr); 354 if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) || 355 (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) { 356 /* 357 * This bit is set when Tx FIFO has < THRESHOLD entries. We have 358 * the THRESHOLD value set to 1, so this bit indicates Tx FIFO 359 * is empty 360 */ 361 rxcount = priv->bytes_to_receive - priv->bytes_to_transfer; 362 rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4); 363 while ((rxindex < rxcount) && 364 (rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) { 365 /* Read out the data from the RX FIFO */ 366 u32 data; 367 data = readl(®s->drxr); 368 369 if (priv->bytes_to_receive >= 4) { 370 if (priv->rx_buf) { 371 memcpy(priv->rx_buf, &data, 4); 372 priv->rx_buf += 4; 373 } 374 priv->bytes_to_receive -= 4; 375 } else { 376 zynq_qspi_read_data(priv, data, 377 priv->bytes_to_receive); 378 } 379 rxindex++; 380 } 381 382 if (priv->bytes_to_transfer) { 383 /* There is more data to send */ 384 zynq_qspi_fill_tx_fifo(priv, 385 ZYNQ_QSPI_RXFIFO_THRESHOLD); 386 387 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier); 388 } else { 389 /* 390 * If transfer and receive is completed then only send 391 * complete signal 392 */ 393 if (!priv->bytes_to_receive) { 394 /* return operation complete */ 395 writel(ZYNQ_QSPI_IXR_ALL_MASK, 396 ®s->idr); 397 return 1; 398 } 399 } 400 } 401 402 return 0; 403 } 404 405 /* 406 * zynq_qspi_start_transfer - Initiates the QSPI transfer 407 * @qspi: Pointer to the spi_device structure 408 * @transfer: Pointer to the spi_transfer structure which provide information 409 * about next transfer parameters 410 * 411 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the 412 * transfer to be completed. 413 * 414 * returns: Number of bytes transferred in the last transfer 415 */ 416 static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv) 417 { 418 u32 data = 0; 419 struct zynq_qspi_regs *regs = priv->regs; 420 421 debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__, 422 (u32)priv, (u32)priv, priv->len); 423 424 priv->bytes_to_transfer = priv->len; 425 priv->bytes_to_receive = priv->len; 426 427 if (priv->len < 4) 428 zynq_qspi_fill_tx_fifo(priv, priv->len); 429 else 430 zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth); 431 432 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier); 433 434 /* wait for completion */ 435 do { 436 data = zynq_qspi_irq_poll(priv); 437 } while (data == 0); 438 439 return (priv->len) - (priv->bytes_to_transfer); 440 } 441 442 static int zynq_qspi_transfer(struct zynq_qspi_priv *priv) 443 { 444 unsigned cs_change = 1; 445 int status = 0; 446 447 while (1) { 448 /* Select the chip if required */ 449 if (cs_change) 450 zynq_qspi_chipselect(priv, 1); 451 452 cs_change = priv->cs_change; 453 454 if (!priv->tx_buf && !priv->rx_buf && priv->len) { 455 status = -1; 456 break; 457 } 458 459 /* Request the transfer */ 460 if (priv->len) { 461 status = zynq_qspi_start_transfer(priv); 462 priv->is_inst = 0; 463 } 464 465 if (status != priv->len) { 466 if (status > 0) 467 status = -EMSGSIZE; 468 debug("zynq_qspi_transfer:%d len:%d\n", 469 status, priv->len); 470 break; 471 } 472 status = 0; 473 474 if (cs_change) 475 /* Deselect the chip */ 476 zynq_qspi_chipselect(priv, 0); 477 478 break; 479 } 480 481 return 0; 482 } 483 484 static int zynq_qspi_claim_bus(struct udevice *dev) 485 { 486 struct udevice *bus = dev->parent; 487 struct zynq_qspi_priv *priv = dev_get_priv(bus); 488 struct zynq_qspi_regs *regs = priv->regs; 489 490 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); 491 492 return 0; 493 } 494 495 static int zynq_qspi_release_bus(struct udevice *dev) 496 { 497 struct udevice *bus = dev->parent; 498 struct zynq_qspi_priv *priv = dev_get_priv(bus); 499 struct zynq_qspi_regs *regs = priv->regs; 500 501 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); 502 503 return 0; 504 } 505 506 static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen, 507 const void *dout, void *din, unsigned long flags) 508 { 509 struct udevice *bus = dev->parent; 510 struct zynq_qspi_priv *priv = dev_get_priv(bus); 511 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 512 513 priv->cs = slave_plat->cs; 514 priv->tx_buf = dout; 515 priv->rx_buf = din; 516 priv->len = bitlen / 8; 517 518 debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", 519 bus->seq, slave_plat->cs, bitlen, priv->len, flags); 520 521 /* 522 * Festering sore. 523 * Assume that the beginning of a transfer with bits to 524 * transmit must contain a device command. 525 */ 526 if (dout && flags & SPI_XFER_BEGIN) 527 priv->is_inst = 1; 528 else 529 priv->is_inst = 0; 530 531 if (flags & SPI_XFER_END) 532 priv->cs_change = 1; 533 else 534 priv->cs_change = 0; 535 536 zynq_qspi_transfer(priv); 537 538 return 0; 539 } 540 541 static int zynq_qspi_set_speed(struct udevice *bus, uint speed) 542 { 543 struct zynq_qspi_platdata *plat = bus->platdata; 544 struct zynq_qspi_priv *priv = dev_get_priv(bus); 545 struct zynq_qspi_regs *regs = priv->regs; 546 uint32_t confr; 547 u8 baud_rate_val = 0; 548 549 if (speed > plat->frequency) 550 speed = plat->frequency; 551 552 /* Set the clock frequency */ 553 confr = readl(®s->cr); 554 if (speed == 0) { 555 /* Set baudrate x8, if the freq is 0 */ 556 baud_rate_val = 0x2; 557 } else if (plat->speed_hz != speed) { 558 while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) && 559 ((plat->frequency / 560 (2 << baud_rate_val)) > speed)) 561 baud_rate_val++; 562 563 plat->speed_hz = speed / (2 << baud_rate_val); 564 } 565 confr &= ~ZYNQ_QSPI_CR_BAUD_MASK; 566 confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT); 567 568 writel(confr, ®s->cr); 569 priv->freq = speed; 570 571 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); 572 573 return 0; 574 } 575 576 static int zynq_qspi_set_mode(struct udevice *bus, uint mode) 577 { 578 struct zynq_qspi_priv *priv = dev_get_priv(bus); 579 struct zynq_qspi_regs *regs = priv->regs; 580 uint32_t confr; 581 582 /* Set the SPI Clock phase and polarities */ 583 confr = readl(®s->cr); 584 confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK); 585 586 if (mode & SPI_CPHA) 587 confr |= ZYNQ_QSPI_CR_CPHA_MASK; 588 if (mode & SPI_CPOL) 589 confr |= ZYNQ_QSPI_CR_CPOL_MASK; 590 591 writel(confr, ®s->cr); 592 priv->mode = mode; 593 594 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); 595 596 return 0; 597 } 598 599 static const struct dm_spi_ops zynq_qspi_ops = { 600 .claim_bus = zynq_qspi_claim_bus, 601 .release_bus = zynq_qspi_release_bus, 602 .xfer = zynq_qspi_xfer, 603 .set_speed = zynq_qspi_set_speed, 604 .set_mode = zynq_qspi_set_mode, 605 }; 606 607 static const struct udevice_id zynq_qspi_ids[] = { 608 { .compatible = "xlnx,zynq-qspi-1.0" }, 609 { } 610 }; 611 612 U_BOOT_DRIVER(zynq_qspi) = { 613 .name = "zynq_qspi", 614 .id = UCLASS_SPI, 615 .of_match = zynq_qspi_ids, 616 .ops = &zynq_qspi_ops, 617 .ofdata_to_platdata = zynq_qspi_ofdata_to_platdata, 618 .platdata_auto_alloc_size = sizeof(struct zynq_qspi_platdata), 619 .priv_auto_alloc_size = sizeof(struct zynq_qspi_priv), 620 .probe = zynq_qspi_probe, 621 }; 622