1 /* 2 * Xilinx SPI driver 3 * 4 * supports 8 bit SPI transfers only, with or w/o FIFO 5 * 6 * based on bfin_spi.c, by way of altera_spi.c 7 * Copyright (c) 2005-2008 Analog Devices Inc. 8 * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw> 9 * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca> 10 * Copyright (c) 2012 Stephan Linz <linz@li-pro.net> 11 * 12 * Licensed under the GPL-2 or later. 13 * 14 * [0]: http://www.xilinx.com/support/documentation 15 * 16 * [S]: [0]/ip_documentation/xps_spi.pdf 17 * [0]/ip_documentation/axi_spi_ds742.pdf 18 */ 19 #include <config.h> 20 #include <common.h> 21 #include <malloc.h> 22 #include <spi.h> 23 24 #include "xilinx_spi.h" 25 26 #ifndef CONFIG_SYS_XILINX_SPI_LIST 27 #define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE } 28 #endif 29 30 #ifndef CONFIG_XILINX_SPI_IDLE_VAL 31 #define CONFIG_XILINX_SPI_IDLE_VAL 0xff 32 #endif 33 34 #define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | \ 35 SPICR_MASTER_MODE | \ 36 SPICR_SPE) 37 38 #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | \ 39 SPICR_MANUAL_SS) 40 41 #define XILSPI_MAX_XFER_BITS 8 42 43 static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST; 44 45 __attribute__((weak)) 46 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 47 { 48 return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32; 49 } 50 51 __attribute__((weak)) 52 void spi_cs_activate(struct spi_slave *slave) 53 { 54 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); 55 56 writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr); 57 } 58 59 __attribute__((weak)) 60 void spi_cs_deactivate(struct spi_slave *slave) 61 { 62 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); 63 64 writel(SPISSR_OFF, &xilspi->regs->spissr); 65 } 66 67 void spi_init(void) 68 { 69 /* do nothing */ 70 } 71 72 void spi_set_speed(struct spi_slave *slave, uint hz) 73 { 74 /* xilinx spi core does not support programmable speed */ 75 } 76 77 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 78 unsigned int max_hz, unsigned int mode) 79 { 80 struct xilinx_spi_slave *xilspi; 81 82 if (!spi_cs_is_valid(bus, cs)) { 83 printf("XILSPI error: %s: unsupported bus %d / cs %d\n", 84 __func__, bus, cs); 85 return NULL; 86 } 87 88 xilspi = malloc(sizeof(*xilspi)); 89 if (!xilspi) { 90 printf("XILSPI error: %s: malloc of SPI structure failed\n", 91 __func__); 92 return NULL; 93 } 94 xilspi->slave.bus = bus; 95 xilspi->slave.cs = cs; 96 xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus]; 97 xilspi->freq = max_hz; 98 xilspi->mode = mode; 99 debug("%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", __func__, 100 bus, cs, xilspi->regs, xilspi->mode, xilspi->freq); 101 102 return &xilspi->slave; 103 } 104 105 void spi_free_slave(struct spi_slave *slave) 106 { 107 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); 108 109 free(xilspi); 110 } 111 112 int spi_claim_bus(struct spi_slave *slave) 113 { 114 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); 115 u32 spicr; 116 117 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); 118 writel(SPISSR_OFF, &xilspi->regs->spissr); 119 120 spicr = XILSPI_SPICR_DFLT_ON; 121 if (xilspi->mode & SPI_LSB_FIRST) 122 spicr |= SPICR_LSB_FIRST; 123 if (xilspi->mode & SPI_CPHA) 124 spicr |= SPICR_CPHA; 125 if (xilspi->mode & SPI_CPOL) 126 spicr |= SPICR_CPOL; 127 if (xilspi->mode & SPI_LOOP) 128 spicr |= SPICR_LOOP; 129 130 writel(spicr, &xilspi->regs->spicr); 131 return 0; 132 } 133 134 void spi_release_bus(struct spi_slave *slave) 135 { 136 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); 137 138 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); 139 writel(SPISSR_OFF, &xilspi->regs->spissr); 140 writel(XILSPI_SPICR_DFLT_OFF, &xilspi->regs->spicr); 141 } 142 143 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 144 void *din, unsigned long flags) 145 { 146 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); 147 /* assume spi core configured to do 8 bit transfers */ 148 unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS; 149 const unsigned char *txp = dout; 150 unsigned char *rxp = din; 151 unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */ 152 153 debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, 154 slave->bus, slave->cs, bitlen, bytes, flags); 155 if (bitlen == 0) 156 goto done; 157 158 if (bitlen % XILSPI_MAX_XFER_BITS) { 159 printf("XILSPI warning: %s: Not a multiple of %d bits\n", 160 __func__, XILSPI_MAX_XFER_BITS); 161 flags |= SPI_XFER_END; 162 goto done; 163 } 164 165 /* empty read buffer */ 166 while (rxecount && !(readl(&xilspi->regs->spisr) & SPISR_RX_EMPTY)) { 167 readl(&xilspi->regs->spidrr); 168 rxecount--; 169 } 170 171 if (!rxecount) { 172 printf("XILSPI error: %s: Rx buffer not empty\n", __func__); 173 return -1; 174 } 175 176 if (flags & SPI_XFER_BEGIN) 177 spi_cs_activate(slave); 178 179 while (bytes--) { 180 unsigned timeout = /* at least 1usec or greater, leftover 1 */ 181 xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 : 182 (XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1; 183 184 /* get Tx element from data out buffer and count up */ 185 unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; 186 debug("%s: tx:%x ", __func__, d); 187 188 /* write out and wait for processing (receive data) */ 189 writel(d & SPIDTR_8BIT_MASK, &xilspi->regs->spidtr); 190 while (timeout && readl(&xilspi->regs->spisr) 191 & SPISR_RX_EMPTY) { 192 timeout--; 193 udelay(1); 194 } 195 196 if (!timeout) { 197 printf("XILSPI error: %s: Xfer timeout\n", __func__); 198 return -1; 199 } 200 201 /* read Rx element and push into data in buffer */ 202 d = readl(&xilspi->regs->spidrr) & SPIDRR_8BIT_MASK; 203 if (rxp) 204 *rxp++ = d; 205 debug("rx:%x\n", d); 206 } 207 208 done: 209 if (flags & SPI_XFER_END) 210 spi_cs_deactivate(slave); 211 212 return 0; 213 } 214