1 /* 2 * Xilinx SPI driver 3 * 4 * Supports 8 bit SPI transfers only, with or w/o FIFO 5 * 6 * Based on bfin_spi.c, by way of altera_spi.c 7 * Copyright (c) 2012 Stephan Linz <linz@li-pro.net> 8 * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca> 9 * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw> 10 * Copyright (c) 2005-2008 Analog Devices Inc. 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <config.h> 16 #include <common.h> 17 #include <malloc.h> 18 #include <spi.h> 19 20 /* 21 * [0]: http://www.xilinx.com/support/documentation 22 * 23 * Xilinx SPI Register Definitions 24 * [1]: [0]/ip_documentation/xps_spi.pdf 25 * page 8, Register Descriptions 26 * [2]: [0]/ip_documentation/axi_spi_ds742.pdf 27 * page 7, Register Overview Table 28 */ 29 30 /* SPI Control Register (spicr), [1] p9, [2] p8 */ 31 #define SPICR_LSB_FIRST (1 << 9) 32 #define SPICR_MASTER_INHIBIT (1 << 8) 33 #define SPICR_MANUAL_SS (1 << 7) 34 #define SPICR_RXFIFO_RESEST (1 << 6) 35 #define SPICR_TXFIFO_RESEST (1 << 5) 36 #define SPICR_CPHA (1 << 4) 37 #define SPICR_CPOL (1 << 3) 38 #define SPICR_MASTER_MODE (1 << 2) 39 #define SPICR_SPE (1 << 1) 40 #define SPICR_LOOP (1 << 0) 41 42 /* SPI Status Register (spisr), [1] p11, [2] p10 */ 43 #define SPISR_SLAVE_MODE_SELECT (1 << 5) 44 #define SPISR_MODF (1 << 4) 45 #define SPISR_TX_FULL (1 << 3) 46 #define SPISR_TX_EMPTY (1 << 2) 47 #define SPISR_RX_FULL (1 << 1) 48 #define SPISR_RX_EMPTY (1 << 0) 49 50 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */ 51 #define SPIDTR_8BIT_MASK (0xff << 0) 52 #define SPIDTR_16BIT_MASK (0xffff << 0) 53 #define SPIDTR_32BIT_MASK (0xffffffff << 0) 54 55 /* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */ 56 #define SPIDRR_8BIT_MASK (0xff << 0) 57 #define SPIDRR_16BIT_MASK (0xffff << 0) 58 #define SPIDRR_32BIT_MASK (0xffffffff << 0) 59 60 /* SPI Slave Select Register (spissr), [1] p13, [2] p13 */ 61 #define SPISSR_MASK(cs) (1 << (cs)) 62 #define SPISSR_ACT(cs) ~SPISSR_MASK(cs) 63 #define SPISSR_OFF ~0UL 64 65 /* SPI Software Reset Register (ssr) */ 66 #define SPISSR_RESET_VALUE 0x0a 67 68 #define XILSPI_MAX_XFER_BITS 8 69 #define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \ 70 SPICR_SPE) 71 #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS) 72 73 #ifndef CONFIG_XILINX_SPI_IDLE_VAL 74 #define CONFIG_XILINX_SPI_IDLE_VAL 0xff 75 #endif 76 77 #ifndef CONFIG_SYS_XILINX_SPI_LIST 78 #define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE } 79 #endif 80 81 /* xilinx spi register set */ 82 struct xilinx_spi_reg { 83 u32 __space0__[7]; 84 u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */ 85 u32 ipisr; /* IP Interrupt Status Register (IPISR) */ 86 u32 __space1__; 87 u32 ipier; /* IP Interrupt Enable Register (IPIER) */ 88 u32 __space2__[5]; 89 u32 srr; /* Softare Reset Register (SRR) */ 90 u32 __space3__[7]; 91 u32 spicr; /* SPI Control Register (SPICR) */ 92 u32 spisr; /* SPI Status Register (SPISR) */ 93 u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */ 94 u32 spidrr; /* SPI Data Receive Register (SPIDRR) */ 95 u32 spissr; /* SPI Slave Select Register (SPISSR) */ 96 u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */ 97 u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */ 98 }; 99 100 /* xilinx spi slave */ 101 struct xilinx_spi_slave { 102 struct spi_slave slave; 103 struct xilinx_spi_reg *regs; 104 unsigned int freq; 105 unsigned int mode; 106 }; 107 108 static inline struct xilinx_spi_slave *to_xilinx_spi_slave( 109 struct spi_slave *slave) 110 { 111 return container_of(slave, struct xilinx_spi_slave, slave); 112 } 113 114 static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST; 115 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 116 { 117 return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32; 118 } 119 120 void spi_cs_activate(struct spi_slave *slave) 121 { 122 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); 123 124 writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr); 125 } 126 127 void spi_cs_deactivate(struct spi_slave *slave) 128 { 129 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); 130 131 writel(SPISSR_OFF, &xilspi->regs->spissr); 132 } 133 134 void spi_init(void) 135 { 136 /* do nothing */ 137 } 138 139 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 140 unsigned int max_hz, unsigned int mode) 141 { 142 struct xilinx_spi_slave *xilspi; 143 144 if (!spi_cs_is_valid(bus, cs)) { 145 printf("XILSPI error: unsupported bus %d / cs %d\n", bus, cs); 146 return NULL; 147 } 148 149 xilspi = spi_alloc_slave(struct xilinx_spi_slave, bus, cs); 150 if (!xilspi) { 151 printf("XILSPI error: malloc of SPI structure failed\n"); 152 return NULL; 153 } 154 xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus]; 155 xilspi->freq = max_hz; 156 xilspi->mode = mode; 157 debug("spi_setup_slave: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", 158 bus, cs, xilspi->regs, xilspi->mode, xilspi->freq); 159 160 writel(SPISSR_RESET_VALUE, &xilspi->regs->srr); 161 162 return &xilspi->slave; 163 } 164 165 void spi_free_slave(struct spi_slave *slave) 166 { 167 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); 168 169 free(xilspi); 170 } 171 172 int spi_claim_bus(struct spi_slave *slave) 173 { 174 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); 175 u32 spicr; 176 177 debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs); 178 writel(SPISSR_OFF, &xilspi->regs->spissr); 179 180 spicr = XILSPI_SPICR_DFLT_ON; 181 if (xilspi->mode & SPI_LSB_FIRST) 182 spicr |= SPICR_LSB_FIRST; 183 if (xilspi->mode & SPI_CPHA) 184 spicr |= SPICR_CPHA; 185 if (xilspi->mode & SPI_CPOL) 186 spicr |= SPICR_CPOL; 187 if (xilspi->mode & SPI_LOOP) 188 spicr |= SPICR_LOOP; 189 190 writel(spicr, &xilspi->regs->spicr); 191 return 0; 192 } 193 194 void spi_release_bus(struct spi_slave *slave) 195 { 196 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); 197 198 debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs); 199 writel(SPISSR_OFF, &xilspi->regs->spissr); 200 writel(XILSPI_SPICR_DFLT_OFF, &xilspi->regs->spicr); 201 } 202 203 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 204 void *din, unsigned long flags) 205 { 206 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); 207 /* assume spi core configured to do 8 bit transfers */ 208 unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS; 209 const unsigned char *txp = dout; 210 unsigned char *rxp = din; 211 unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */ 212 unsigned global_timeout; 213 214 debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", 215 slave->bus, slave->cs, bitlen, bytes, flags); 216 217 if (bitlen == 0) 218 goto done; 219 220 if (bitlen % XILSPI_MAX_XFER_BITS) { 221 printf("XILSPI warning: Not a multiple of %d bits\n", 222 XILSPI_MAX_XFER_BITS); 223 flags |= SPI_XFER_END; 224 goto done; 225 } 226 227 /* empty read buffer */ 228 while (rxecount && !(readl(&xilspi->regs->spisr) & SPISR_RX_EMPTY)) { 229 readl(&xilspi->regs->spidrr); 230 rxecount--; 231 } 232 233 if (!rxecount) { 234 printf("XILSPI error: Rx buffer not empty\n"); 235 return -1; 236 } 237 238 if (flags & SPI_XFER_BEGIN) 239 spi_cs_activate(slave); 240 241 /* at least 1usec or greater, leftover 1 */ 242 global_timeout = xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 : 243 (XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1; 244 245 while (bytes--) { 246 unsigned timeout = global_timeout; 247 /* get Tx element from data out buffer and count up */ 248 unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; 249 debug("spi_xfer: tx:%x ", d); 250 251 /* write out and wait for processing (receive data) */ 252 writel(d & SPIDTR_8BIT_MASK, &xilspi->regs->spidtr); 253 while (timeout && readl(&xilspi->regs->spisr) 254 & SPISR_RX_EMPTY) { 255 timeout--; 256 udelay(1); 257 } 258 259 if (!timeout) { 260 printf("XILSPI error: Xfer timeout\n"); 261 return -1; 262 } 263 264 /* read Rx element and push into data in buffer */ 265 d = readl(&xilspi->regs->spidrr) & SPIDRR_8BIT_MASK; 266 if (rxp) 267 *rxp++ = d; 268 debug("spi_xfer: rx:%x\n", d); 269 } 270 271 done: 272 if (flags & SPI_XFER_END) 273 spi_cs_deactivate(slave); 274 275 return 0; 276 } 277