1 /* 2 * TI QSPI driver 3 * 4 * Copyright (C) 2013, Texas Instruments, Incorporated 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/omap.h> 12 #include <malloc.h> 13 #include <spi.h> 14 #include <asm/gpio.h> 15 #include <asm/omap_gpio.h> 16 17 /* ti qpsi register bit masks */ 18 #define QSPI_TIMEOUT 2000000 19 #define QSPI_FCLK 192000000 20 /* clock control */ 21 #define QSPI_CLK_EN (1 << 31) 22 #define QSPI_CLK_DIV_MAX 0xffff 23 /* command */ 24 #define QSPI_EN_CS(n) (n << 28) 25 #define QSPI_WLEN(n) ((n-1) << 19) 26 #define QSPI_3_PIN (1 << 18) 27 #define QSPI_RD_SNGL (1 << 16) 28 #define QSPI_WR_SNGL (2 << 16) 29 #define QSPI_INVAL (4 << 16) 30 #define QSPI_RD_QUAD (7 << 16) 31 /* device control */ 32 #define QSPI_DD(m, n) (m << (3 + n*8)) 33 #define QSPI_CKPHA(n) (1 << (2 + n*8)) 34 #define QSPI_CSPOL(n) (1 << (1 + n*8)) 35 #define QSPI_CKPOL(n) (1 << (n*8)) 36 /* status */ 37 #define QSPI_WC (1 << 1) 38 #define QSPI_BUSY (1 << 0) 39 #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) 40 #define QSPI_XFER_DONE QSPI_WC 41 #define MM_SWITCH 0x01 42 #define MEM_CS 0x100 43 #define MEM_CS_UNSELECT 0xfffff0ff 44 #define MMAP_START_ADDR_DRA 0x5c000000 45 #define MMAP_START_ADDR_AM43x 0x30000000 46 #define CORE_CTRL_IO 0x4a002558 47 48 #define QSPI_CMD_READ (0x3 << 0) 49 #define QSPI_CMD_READ_QUAD (0x6b << 0) 50 #define QSPI_CMD_READ_FAST (0x0b << 0) 51 #define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) 52 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10) 53 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10) 54 #define QSPI_SETUP0_READ_NORMAL (0x0 << 12) 55 #define QSPI_SETUP0_READ_QUAD (0x3 << 12) 56 #define QSPI_CMD_WRITE (0x2 << 16) 57 #define QSPI_NUM_DUMMY_BITS (0x0 << 24) 58 59 /* ti qspi register set */ 60 struct ti_qspi_regs { 61 u32 pid; 62 u32 pad0[3]; 63 u32 sysconfig; 64 u32 pad1[3]; 65 u32 int_stat_raw; 66 u32 int_stat_en; 67 u32 int_en_set; 68 u32 int_en_ctlr; 69 u32 intc_eoi; 70 u32 pad2[3]; 71 u32 clk_ctrl; 72 u32 dc; 73 u32 cmd; 74 u32 status; 75 u32 data; 76 u32 setup0; 77 u32 setup1; 78 u32 setup2; 79 u32 setup3; 80 u32 memswitch; 81 u32 data1; 82 u32 data2; 83 u32 data3; 84 }; 85 86 /* ti qspi slave */ 87 struct ti_qspi_slave { 88 struct spi_slave slave; 89 struct ti_qspi_regs *base; 90 unsigned int mode; 91 u32 cmd; 92 u32 dc; 93 }; 94 95 static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave) 96 { 97 return container_of(slave, struct ti_qspi_slave, slave); 98 } 99 100 static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) 101 { 102 struct spi_slave *slave = &qslave->slave; 103 u32 memval = 0; 104 105 #ifdef CONFIG_DRA7XX 106 slave->memory_map = (void *)MMAP_START_ADDR_DRA; 107 #else 108 slave->memory_map = (void *)MMAP_START_ADDR_AM43x; 109 #endif 110 111 memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | 112 QSPI_SETUP0_NUM_D_BYTES_NO_BITS | 113 QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | 114 QSPI_NUM_DUMMY_BITS; 115 116 writel(memval, &qslave->base->setup0); 117 } 118 119 static void ti_spi_set_speed(struct spi_slave *slave, uint hz) 120 { 121 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); 122 uint clk_div; 123 124 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); 125 126 if (!hz) 127 clk_div = 0; 128 else 129 clk_div = (QSPI_FCLK / hz) - 1; 130 131 /* disable SCLK */ 132 writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN, 133 &qslave->base->clk_ctrl); 134 135 /* assign clk_div values */ 136 if (clk_div < 0) 137 clk_div = 0; 138 else if (clk_div > QSPI_CLK_DIV_MAX) 139 clk_div = QSPI_CLK_DIV_MAX; 140 141 /* enable SCLK */ 142 writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl); 143 } 144 145 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 146 { 147 return 1; 148 } 149 150 void spi_cs_activate(struct spi_slave *slave) 151 { 152 /* CS handled in xfer */ 153 return; 154 } 155 156 void spi_cs_deactivate(struct spi_slave *slave) 157 { 158 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); 159 160 debug("spi_cs_deactivate: 0x%08x\n", (u32)slave); 161 162 writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd); 163 } 164 165 void spi_init(void) 166 { 167 /* nothing to do */ 168 } 169 170 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 171 unsigned int max_hz, unsigned int mode) 172 { 173 struct ti_qspi_slave *qslave; 174 175 #ifdef CONFIG_AM43XX 176 gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); 177 gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); 178 #endif 179 180 qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs); 181 if (!qslave) { 182 printf("SPI_error: Fail to allocate ti_qspi_slave\n"); 183 return NULL; 184 } 185 186 qslave->base = (struct ti_qspi_regs *)QSPI_BASE; 187 qslave->mode = mode; 188 189 ti_spi_set_speed(&qslave->slave, max_hz); 190 191 #ifdef CONFIG_TI_SPI_MMAP 192 ti_spi_setup_spi_register(qslave); 193 #endif 194 195 return &qslave->slave; 196 } 197 198 void spi_free_slave(struct spi_slave *slave) 199 { 200 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); 201 free(qslave); 202 } 203 204 int spi_claim_bus(struct spi_slave *slave) 205 { 206 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); 207 208 debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs); 209 210 qslave->dc = 0; 211 if (qslave->mode & SPI_CPHA) 212 qslave->dc |= QSPI_CKPHA(slave->cs); 213 if (qslave->mode & SPI_CPOL) 214 qslave->dc |= QSPI_CKPOL(slave->cs); 215 if (qslave->mode & SPI_CS_HIGH) 216 qslave->dc |= QSPI_CSPOL(slave->cs); 217 218 writel(qslave->dc, &qslave->base->dc); 219 writel(0, &qslave->base->cmd); 220 writel(0, &qslave->base->data); 221 222 return 0; 223 } 224 225 void spi_release_bus(struct spi_slave *slave) 226 { 227 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); 228 229 debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs); 230 231 writel(0, &qslave->base->dc); 232 writel(0, &qslave->base->cmd); 233 writel(0, &qslave->base->data); 234 } 235 236 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 237 void *din, unsigned long flags) 238 { 239 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); 240 uint words = bitlen >> 3; /* fixed 8-bit word length */ 241 const uchar *txp = dout; 242 uchar *rxp = din; 243 uint status; 244 int timeout; 245 246 #ifdef CONFIG_DRA7XX 247 int val; 248 #endif 249 250 debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", 251 slave->bus, slave->cs, bitlen, words, flags); 252 253 /* Setup mmap flags */ 254 if (flags & SPI_XFER_MMAP) { 255 writel(MM_SWITCH, &qslave->base->memswitch); 256 #ifdef CONFIG_DRA7XX 257 val = readl(CORE_CTRL_IO); 258 val |= MEM_CS; 259 writel(val, CORE_CTRL_IO); 260 #endif 261 return 0; 262 } else if (flags & SPI_XFER_MMAP_END) { 263 writel(~MM_SWITCH, &qslave->base->memswitch); 264 #ifdef CONFIG_DRA7XX 265 val = readl(CORE_CTRL_IO); 266 val &= MEM_CS_UNSELECT; 267 writel(val, CORE_CTRL_IO); 268 #endif 269 return 0; 270 } 271 272 if (bitlen == 0) 273 return -1; 274 275 if (bitlen % 8) { 276 debug("spi_xfer: Non byte aligned SPI transfer\n"); 277 return -1; 278 } 279 280 /* Setup command reg */ 281 qslave->cmd = 0; 282 qslave->cmd |= QSPI_WLEN(8); 283 qslave->cmd |= QSPI_EN_CS(slave->cs); 284 if (flags & SPI_3WIRE) 285 qslave->cmd |= QSPI_3_PIN; 286 qslave->cmd |= 0xfff; 287 288 /* FIXME: This delay is required for successfull 289 * completion of read/write/erase. Once its root 290 * caused, it will be remove from the driver. 291 */ 292 #ifdef CONFIG_AM43XX 293 udelay(100); 294 #endif 295 while (words--) { 296 if (txp) { 297 debug("tx cmd %08x dc %08x data %02x\n", 298 qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp); 299 writel(*txp++, &qslave->base->data); 300 writel(qslave->cmd | QSPI_WR_SNGL, 301 &qslave->base->cmd); 302 status = readl(&qslave->base->status); 303 timeout = QSPI_TIMEOUT; 304 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { 305 if (--timeout < 0) { 306 printf("spi_xfer: TX timeout!\n"); 307 return -1; 308 } 309 status = readl(&qslave->base->status); 310 } 311 debug("tx done, status %08x\n", status); 312 } 313 if (rxp) { 314 qslave->cmd |= QSPI_RD_SNGL; 315 debug("rx cmd %08x dc %08x\n", 316 qslave->cmd, qslave->dc); 317 #ifdef CONFIG_DRA7XX 318 udelay(500); 319 #endif 320 writel(qslave->cmd, &qslave->base->cmd); 321 status = readl(&qslave->base->status); 322 timeout = QSPI_TIMEOUT; 323 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { 324 if (--timeout < 0) { 325 printf("spi_xfer: RX timeout!\n"); 326 return -1; 327 } 328 status = readl(&qslave->base->status); 329 } 330 *rxp++ = readl(&qslave->base->data); 331 debug("rx done, status %08x, read %02x\n", 332 status, *(rxp-1)); 333 } 334 } 335 336 /* Terminate frame */ 337 if (flags & SPI_XFER_END) 338 spi_cs_deactivate(slave); 339 340 return 0; 341 } 342