1 /* 2 * TI QSPI driver 3 * 4 * Copyright (C) 2013, Texas Instruments, Incorporated 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/omap.h> 12 #include <malloc.h> 13 #include <spi.h> 14 #include <dm.h> 15 #include <asm/gpio.h> 16 #include <asm/omap_gpio.h> 17 #include <asm/omap_common.h> 18 #include <asm/ti-common/ti-edma3.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 /* ti qpsi register bit masks */ 23 #define QSPI_TIMEOUT 2000000 24 #define QSPI_FCLK 192000000 25 #define QSPI_DRA7XX_FCLK 76800000 26 /* clock control */ 27 #define QSPI_CLK_EN BIT(31) 28 #define QSPI_CLK_DIV_MAX 0xffff 29 /* command */ 30 #define QSPI_EN_CS(n) (n << 28) 31 #define QSPI_WLEN(n) ((n-1) << 19) 32 #define QSPI_3_PIN BIT(18) 33 #define QSPI_RD_SNGL BIT(16) 34 #define QSPI_WR_SNGL (2 << 16) 35 #define QSPI_INVAL (4 << 16) 36 #define QSPI_RD_QUAD (7 << 16) 37 /* device control */ 38 #define QSPI_DD(m, n) (m << (3 + n*8)) 39 #define QSPI_CKPHA(n) (1 << (2 + n*8)) 40 #define QSPI_CSPOL(n) (1 << (1 + n*8)) 41 #define QSPI_CKPOL(n) (1 << (n*8)) 42 /* status */ 43 #define QSPI_WC BIT(1) 44 #define QSPI_BUSY BIT(0) 45 #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) 46 #define QSPI_XFER_DONE QSPI_WC 47 #define MM_SWITCH 0x01 48 #define MEM_CS(cs) ((cs + 1) << 8) 49 #define MEM_CS_UNSELECT 0xfffff8ff 50 #define MMAP_START_ADDR_DRA 0x5c000000 51 #define MMAP_START_ADDR_AM43x 0x30000000 52 #define CORE_CTRL_IO 0x4a002558 53 54 #define QSPI_CMD_READ (0x3 << 0) 55 #define QSPI_CMD_READ_DUAL (0x6b << 0) 56 #define QSPI_CMD_READ_QUAD (0x6c << 0) 57 #define QSPI_CMD_READ_FAST (0x0b << 0) 58 #define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8) 59 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10) 60 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10) 61 #define QSPI_SETUP0_READ_NORMAL (0x0 << 12) 62 #define QSPI_SETUP0_READ_DUAL (0x1 << 12) 63 #define QSPI_SETUP0_READ_QUAD (0x3 << 12) 64 #define QSPI_CMD_WRITE (0x12 << 16) 65 #define QSPI_NUM_DUMMY_BITS (0x0 << 24) 66 67 /* ti qspi register set */ 68 struct ti_qspi_regs { 69 u32 pid; 70 u32 pad0[3]; 71 u32 sysconfig; 72 u32 pad1[3]; 73 u32 int_stat_raw; 74 u32 int_stat_en; 75 u32 int_en_set; 76 u32 int_en_ctlr; 77 u32 intc_eoi; 78 u32 pad2[3]; 79 u32 clk_ctrl; 80 u32 dc; 81 u32 cmd; 82 u32 status; 83 u32 data; 84 u32 setup0; 85 u32 setup1; 86 u32 setup2; 87 u32 setup3; 88 u32 memswitch; 89 u32 data1; 90 u32 data2; 91 u32 data3; 92 }; 93 94 /* ti qspi priv */ 95 struct ti_qspi_priv { 96 #ifndef CONFIG_DM_SPI 97 struct spi_slave slave; 98 #else 99 void *memory_map; 100 uint max_hz; 101 u32 num_cs; 102 #endif 103 struct ti_qspi_regs *base; 104 void *ctrl_mod_mmap; 105 ulong fclk; 106 unsigned int mode; 107 u32 cmd; 108 u32 dc; 109 }; 110 111 static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) 112 { 113 uint clk_div; 114 115 if (!hz) 116 clk_div = 0; 117 else 118 clk_div = (priv->fclk / hz) - 1; 119 120 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); 121 122 /* disable SCLK */ 123 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, 124 &priv->base->clk_ctrl); 125 126 /* assign clk_div values */ 127 if (clk_div < 0) 128 clk_div = 0; 129 else if (clk_div > QSPI_CLK_DIV_MAX) 130 clk_div = QSPI_CLK_DIV_MAX; 131 132 /* enable SCLK */ 133 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); 134 } 135 136 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv) 137 { 138 writel(priv->cmd | QSPI_INVAL, &priv->base->cmd); 139 /* dummy readl to ensure bus sync */ 140 readl(&priv->base->cmd); 141 } 142 143 static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode) 144 { 145 priv->dc = 0; 146 if (mode & SPI_CPHA) 147 priv->dc |= QSPI_CKPHA(0); 148 if (mode & SPI_CPOL) 149 priv->dc |= QSPI_CKPOL(0); 150 if (mode & SPI_CS_HIGH) 151 priv->dc |= QSPI_CSPOL(0); 152 153 return 0; 154 } 155 156 static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs) 157 { 158 writel(priv->dc, &priv->base->dc); 159 writel(0, &priv->base->cmd); 160 writel(0, &priv->base->data); 161 162 priv->dc <<= cs * 8; 163 writel(priv->dc, &priv->base->dc); 164 165 return 0; 166 } 167 168 static void __ti_qspi_release_bus(struct ti_qspi_priv *priv) 169 { 170 writel(0, &priv->base->dc); 171 writel(0, &priv->base->cmd); 172 writel(0, &priv->base->data); 173 } 174 175 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable) 176 { 177 u32 val; 178 179 val = readl(ctrl_mod_mmap); 180 if (enable) 181 val |= MEM_CS(cs); 182 else 183 val &= MEM_CS_UNSELECT; 184 writel(val, ctrl_mod_mmap); 185 } 186 187 static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, 188 const void *dout, void *din, unsigned long flags, 189 u32 cs) 190 { 191 uint words = bitlen >> 3; /* fixed 8-bit word length */ 192 const uchar *txp = dout; 193 uchar *rxp = din; 194 uint status; 195 int timeout; 196 197 /* Setup mmap flags */ 198 if (flags & SPI_XFER_MMAP) { 199 writel(MM_SWITCH, &priv->base->memswitch); 200 if (priv->ctrl_mod_mmap) 201 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true); 202 return 0; 203 } else if (flags & SPI_XFER_MMAP_END) { 204 writel(~MM_SWITCH, &priv->base->memswitch); 205 if (priv->ctrl_mod_mmap) 206 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false); 207 return 0; 208 } 209 210 if (bitlen == 0) 211 return -1; 212 213 if (bitlen % 8) { 214 debug("spi_xfer: Non byte aligned SPI transfer\n"); 215 return -1; 216 } 217 218 /* Setup command reg */ 219 priv->cmd = 0; 220 priv->cmd |= QSPI_WLEN(8); 221 priv->cmd |= QSPI_EN_CS(cs); 222 if (priv->mode & SPI_3WIRE) 223 priv->cmd |= QSPI_3_PIN; 224 priv->cmd |= 0xfff; 225 226 /* FIXME: This delay is required for successfull 227 * completion of read/write/erase. Once its root 228 * caused, it will be remove from the driver. 229 */ 230 #ifdef CONFIG_AM43XX 231 udelay(100); 232 #endif 233 while (words--) { 234 if (txp) { 235 debug("tx cmd %08x dc %08x data %02x\n", 236 priv->cmd | QSPI_WR_SNGL, priv->dc, *txp); 237 writel(*txp++, &priv->base->data); 238 writel(priv->cmd | QSPI_WR_SNGL, 239 &priv->base->cmd); 240 status = readl(&priv->base->status); 241 timeout = QSPI_TIMEOUT; 242 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { 243 if (--timeout < 0) { 244 printf("spi_xfer: TX timeout!\n"); 245 return -1; 246 } 247 status = readl(&priv->base->status); 248 } 249 debug("tx done, status %08x\n", status); 250 } 251 if (rxp) { 252 debug("rx cmd %08x dc %08x\n", 253 ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc); 254 writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd); 255 status = readl(&priv->base->status); 256 timeout = QSPI_TIMEOUT; 257 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { 258 if (--timeout < 0) { 259 printf("spi_xfer: RX timeout!\n"); 260 return -1; 261 } 262 status = readl(&priv->base->status); 263 } 264 *rxp++ = readl(&priv->base->data); 265 debug("rx done, status %08x, read %02x\n", 266 status, *(rxp-1)); 267 } 268 } 269 270 /* Terminate frame */ 271 if (flags & SPI_XFER_END) 272 ti_qspi_cs_deactivate(priv); 273 274 return 0; 275 } 276 277 /* TODO: control from sf layer to here through dm-spi */ 278 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA) 279 void spi_flash_copy_mmap(void *data, void *offset, size_t len) 280 { 281 unsigned int addr = (unsigned int) (data); 282 unsigned int edma_slot_num = 1; 283 284 /* Invalidate the area, so no writeback into the RAM races with DMA */ 285 invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN)); 286 287 /* enable edma3 clocks */ 288 enable_edma3_clocks(); 289 290 /* Call edma3 api to do actual DMA transfer */ 291 edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len); 292 293 /* disable edma3 clocks */ 294 disable_edma3_clocks(); 295 296 *((unsigned int *)offset) += len; 297 } 298 #endif 299 300 #ifndef CONFIG_DM_SPI 301 302 static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave) 303 { 304 return container_of(slave, struct ti_qspi_priv, slave); 305 } 306 307 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 308 { 309 return 1; 310 } 311 312 void spi_cs_activate(struct spi_slave *slave) 313 { 314 /* CS handled in xfer */ 315 return; 316 } 317 318 void spi_cs_deactivate(struct spi_slave *slave) 319 { 320 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); 321 ti_qspi_cs_deactivate(priv); 322 } 323 324 void spi_init(void) 325 { 326 /* nothing to do */ 327 } 328 329 static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv) 330 { 331 u32 memval = 0; 332 333 #ifdef CONFIG_QSPI_QUAD_SUPPORT 334 struct spi_slave *slave = &priv->slave; 335 memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | 336 QSPI_SETUP0_NUM_D_BYTES_8_BITS | 337 QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | 338 QSPI_NUM_DUMMY_BITS); 339 slave->mode_rx = SPI_RX_QUAD; 340 #else 341 memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | 342 QSPI_SETUP0_NUM_D_BYTES_NO_BITS | 343 QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | 344 QSPI_NUM_DUMMY_BITS; 345 #endif 346 347 writel(memval, &priv->base->setup0); 348 } 349 350 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 351 unsigned int max_hz, unsigned int mode) 352 { 353 struct ti_qspi_priv *priv; 354 355 #ifdef CONFIG_AM43XX 356 gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); 357 gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); 358 #endif 359 360 priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs); 361 if (!priv) { 362 printf("SPI_error: Fail to allocate ti_qspi_priv\n"); 363 return NULL; 364 } 365 366 priv->base = (struct ti_qspi_regs *)QSPI_BASE; 367 priv->mode = mode; 368 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) 369 priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO; 370 priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA; 371 priv->fclk = QSPI_DRA7XX_FCLK; 372 #else 373 priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x; 374 priv->fclk = QSPI_FCLK; 375 #endif 376 377 ti_spi_set_speed(priv, max_hz); 378 379 #ifdef CONFIG_TI_SPI_MMAP 380 ti_spi_setup_spi_register(priv); 381 #endif 382 383 return &priv->slave; 384 } 385 386 void spi_free_slave(struct spi_slave *slave) 387 { 388 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); 389 free(priv); 390 } 391 392 int spi_claim_bus(struct spi_slave *slave) 393 { 394 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); 395 396 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); 397 __ti_qspi_set_mode(priv, priv->mode); 398 return __ti_qspi_claim_bus(priv, priv->slave.cs); 399 } 400 void spi_release_bus(struct spi_slave *slave) 401 { 402 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); 403 404 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); 405 __ti_qspi_release_bus(priv); 406 } 407 408 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 409 void *din, unsigned long flags) 410 { 411 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); 412 413 debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n", 414 priv->slave.bus, priv->slave.cs, bitlen, flags); 415 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs); 416 } 417 418 #else /* CONFIG_DM_SPI */ 419 420 static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv, 421 struct spi_slave *slave, 422 bool enable) 423 { 424 u32 memval; 425 u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL); 426 427 if (!enable) { 428 writel(0, &priv->base->setup0); 429 return; 430 } 431 432 memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS; 433 434 switch (mode) { 435 case SPI_RX_QUAD: 436 memval |= QSPI_CMD_READ_QUAD; 437 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; 438 memval |= QSPI_SETUP0_READ_QUAD; 439 slave->mode_rx = SPI_RX_QUAD; 440 break; 441 case SPI_RX_DUAL: 442 memval |= QSPI_CMD_READ_DUAL; 443 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; 444 memval |= QSPI_SETUP0_READ_DUAL; 445 break; 446 default: 447 memval |= QSPI_CMD_READ; 448 memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS; 449 memval |= QSPI_SETUP0_READ_NORMAL; 450 break; 451 } 452 453 writel(memval, &priv->base->setup0); 454 } 455 456 457 static int ti_qspi_set_speed(struct udevice *bus, uint max_hz) 458 { 459 struct ti_qspi_priv *priv = dev_get_priv(bus); 460 461 ti_spi_set_speed(priv, max_hz); 462 463 return 0; 464 } 465 466 static int ti_qspi_set_mode(struct udevice *bus, uint mode) 467 { 468 struct ti_qspi_priv *priv = dev_get_priv(bus); 469 return __ti_qspi_set_mode(priv, mode); 470 } 471 472 static int ti_qspi_claim_bus(struct udevice *dev) 473 { 474 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 475 struct spi_slave *slave = dev_get_parent_priv(dev); 476 struct ti_qspi_priv *priv; 477 struct udevice *bus; 478 479 bus = dev->parent; 480 priv = dev_get_priv(bus); 481 482 if (slave_plat->cs > priv->num_cs) { 483 debug("invalid qspi chip select\n"); 484 return -EINVAL; 485 } 486 487 __ti_qspi_setup_memorymap(priv, slave, true); 488 489 return __ti_qspi_claim_bus(priv, slave_plat->cs); 490 } 491 492 static int ti_qspi_release_bus(struct udevice *dev) 493 { 494 struct spi_slave *slave = dev_get_parent_priv(dev); 495 struct ti_qspi_priv *priv; 496 struct udevice *bus; 497 498 bus = dev->parent; 499 priv = dev_get_priv(bus); 500 501 __ti_qspi_setup_memorymap(priv, slave, false); 502 __ti_qspi_release_bus(priv); 503 504 return 0; 505 } 506 507 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, 508 const void *dout, void *din, unsigned long flags) 509 { 510 struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); 511 struct ti_qspi_priv *priv; 512 struct udevice *bus; 513 514 bus = dev->parent; 515 priv = dev_get_priv(bus); 516 517 if (slave->cs > priv->num_cs) { 518 debug("invalid qspi chip select\n"); 519 return -EINVAL; 520 } 521 522 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs); 523 } 524 525 static int ti_qspi_probe(struct udevice *bus) 526 { 527 struct ti_qspi_priv *priv = dev_get_priv(bus); 528 529 priv->fclk = dev_get_driver_data(bus); 530 531 return 0; 532 } 533 534 static int ti_qspi_ofdata_to_platdata(struct udevice *bus) 535 { 536 struct ti_qspi_priv *priv = dev_get_priv(bus); 537 const void *blob = gd->fdt_blob; 538 int node = bus->of_offset; 539 fdt_addr_t addr; 540 void *mmap; 541 542 priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs), 543 MAP_NOCACHE); 544 priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0, 545 MAP_NOCACHE); 546 addr = dev_get_addr_index(bus, 2); 547 mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE); 548 priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap; 549 550 priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); 551 if (priv->max_hz < 0) { 552 debug("Error: Max frequency missing\n"); 553 return -ENODEV; 554 } 555 priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4); 556 557 debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__, 558 (int)priv->base, priv->max_hz); 559 560 return 0; 561 } 562 563 static int ti_qspi_child_pre_probe(struct udevice *dev) 564 { 565 struct spi_slave *slave = dev_get_parent_priv(dev); 566 struct udevice *bus = dev_get_parent(dev); 567 struct ti_qspi_priv *priv = dev_get_priv(bus); 568 569 slave->memory_map = priv->memory_map; 570 return 0; 571 } 572 573 static const struct dm_spi_ops ti_qspi_ops = { 574 .claim_bus = ti_qspi_claim_bus, 575 .release_bus = ti_qspi_release_bus, 576 .xfer = ti_qspi_xfer, 577 .set_speed = ti_qspi_set_speed, 578 .set_mode = ti_qspi_set_mode, 579 }; 580 581 static const struct udevice_id ti_qspi_ids[] = { 582 { .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK}, 583 { .compatible = "ti,am4372-qspi", .data = QSPI_FCLK}, 584 { } 585 }; 586 587 U_BOOT_DRIVER(ti_qspi) = { 588 .name = "ti_qspi", 589 .id = UCLASS_SPI, 590 .of_match = ti_qspi_ids, 591 .ops = &ti_qspi_ops, 592 .ofdata_to_platdata = ti_qspi_ofdata_to_platdata, 593 .priv_auto_alloc_size = sizeof(struct ti_qspi_priv), 594 .probe = ti_qspi_probe, 595 .child_pre_probe = ti_qspi_child_pre_probe, 596 }; 597 #endif /* CONFIG_DM_SPI */ 598