1 /* 2 * TI QSPI driver 3 * 4 * Copyright (C) 2013, Texas Instruments, Incorporated 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/omap.h> 12 #include <malloc.h> 13 #include <spi.h> 14 #include <asm/gpio.h> 15 #include <asm/omap_gpio.h> 16 #include <asm/omap_common.h> 17 #include <asm/ti-common/ti-edma3.h> 18 19 /* ti qpsi register bit masks */ 20 #define QSPI_TIMEOUT 2000000 21 #define QSPI_FCLK 192000000 22 /* clock control */ 23 #define QSPI_CLK_EN (1 << 31) 24 #define QSPI_CLK_DIV_MAX 0xffff 25 /* command */ 26 #define QSPI_EN_CS(n) (n << 28) 27 #define QSPI_WLEN(n) ((n-1) << 19) 28 #define QSPI_3_PIN (1 << 18) 29 #define QSPI_RD_SNGL (1 << 16) 30 #define QSPI_WR_SNGL (2 << 16) 31 #define QSPI_INVAL (4 << 16) 32 #define QSPI_RD_QUAD (7 << 16) 33 /* device control */ 34 #define QSPI_DD(m, n) (m << (3 + n*8)) 35 #define QSPI_CKPHA(n) (1 << (2 + n*8)) 36 #define QSPI_CSPOL(n) (1 << (1 + n*8)) 37 #define QSPI_CKPOL(n) (1 << (n*8)) 38 /* status */ 39 #define QSPI_WC (1 << 1) 40 #define QSPI_BUSY (1 << 0) 41 #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) 42 #define QSPI_XFER_DONE QSPI_WC 43 #define MM_SWITCH 0x01 44 #define MEM_CS 0x100 45 #define MEM_CS_UNSELECT 0xfffff0ff 46 #define MMAP_START_ADDR_DRA 0x5c000000 47 #define MMAP_START_ADDR_AM43x 0x30000000 48 #define CORE_CTRL_IO 0x4a002558 49 50 #define QSPI_CMD_READ (0x3 << 0) 51 #define QSPI_CMD_READ_QUAD (0x6b << 0) 52 #define QSPI_CMD_READ_FAST (0x0b << 0) 53 #define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) 54 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10) 55 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10) 56 #define QSPI_SETUP0_READ_NORMAL (0x0 << 12) 57 #define QSPI_SETUP0_READ_QUAD (0x3 << 12) 58 #define QSPI_CMD_WRITE (0x2 << 16) 59 #define QSPI_NUM_DUMMY_BITS (0x0 << 24) 60 61 /* ti qspi register set */ 62 struct ti_qspi_regs { 63 u32 pid; 64 u32 pad0[3]; 65 u32 sysconfig; 66 u32 pad1[3]; 67 u32 int_stat_raw; 68 u32 int_stat_en; 69 u32 int_en_set; 70 u32 int_en_ctlr; 71 u32 intc_eoi; 72 u32 pad2[3]; 73 u32 clk_ctrl; 74 u32 dc; 75 u32 cmd; 76 u32 status; 77 u32 data; 78 u32 setup0; 79 u32 setup1; 80 u32 setup2; 81 u32 setup3; 82 u32 memswitch; 83 u32 data1; 84 u32 data2; 85 u32 data3; 86 }; 87 88 /* ti qspi slave */ 89 struct ti_qspi_slave { 90 struct spi_slave slave; 91 struct ti_qspi_regs *base; 92 unsigned int mode; 93 u32 cmd; 94 u32 dc; 95 }; 96 97 static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave) 98 { 99 return container_of(slave, struct ti_qspi_slave, slave); 100 } 101 102 static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) 103 { 104 struct spi_slave *slave = &qslave->slave; 105 u32 memval = 0; 106 107 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) 108 slave->memory_map = (void *)MMAP_START_ADDR_DRA; 109 #else 110 slave->memory_map = (void *)MMAP_START_ADDR_AM43x; 111 #endif 112 113 #ifdef CONFIG_QSPI_QUAD_SUPPORT 114 memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | 115 QSPI_SETUP0_NUM_D_BYTES_8_BITS | 116 QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | 117 QSPI_NUM_DUMMY_BITS); 118 slave->op_mode_rx = SPI_OPM_RX_QOF; 119 #else 120 memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | 121 QSPI_SETUP0_NUM_D_BYTES_NO_BITS | 122 QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | 123 QSPI_NUM_DUMMY_BITS; 124 #endif 125 126 writel(memval, &qslave->base->setup0); 127 } 128 129 static void ti_spi_set_speed(struct spi_slave *slave, uint hz) 130 { 131 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); 132 uint clk_div; 133 134 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); 135 136 if (!hz) 137 clk_div = 0; 138 else 139 clk_div = (QSPI_FCLK / hz) - 1; 140 141 /* disable SCLK */ 142 writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN, 143 &qslave->base->clk_ctrl); 144 145 /* assign clk_div values */ 146 if (clk_div < 0) 147 clk_div = 0; 148 else if (clk_div > QSPI_CLK_DIV_MAX) 149 clk_div = QSPI_CLK_DIV_MAX; 150 151 /* enable SCLK */ 152 writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl); 153 } 154 155 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 156 { 157 return 1; 158 } 159 160 void spi_cs_activate(struct spi_slave *slave) 161 { 162 /* CS handled in xfer */ 163 return; 164 } 165 166 void spi_cs_deactivate(struct spi_slave *slave) 167 { 168 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); 169 170 debug("spi_cs_deactivate: 0x%08x\n", (u32)slave); 171 172 writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd); 173 } 174 175 void spi_init(void) 176 { 177 /* nothing to do */ 178 } 179 180 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 181 unsigned int max_hz, unsigned int mode) 182 { 183 struct ti_qspi_slave *qslave; 184 185 #ifdef CONFIG_AM43XX 186 gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); 187 gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); 188 #endif 189 190 qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs); 191 if (!qslave) { 192 printf("SPI_error: Fail to allocate ti_qspi_slave\n"); 193 return NULL; 194 } 195 196 qslave->base = (struct ti_qspi_regs *)QSPI_BASE; 197 qslave->mode = mode; 198 199 ti_spi_set_speed(&qslave->slave, max_hz); 200 201 #ifdef CONFIG_TI_SPI_MMAP 202 ti_spi_setup_spi_register(qslave); 203 #endif 204 205 return &qslave->slave; 206 } 207 208 void spi_free_slave(struct spi_slave *slave) 209 { 210 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); 211 free(qslave); 212 } 213 214 int spi_claim_bus(struct spi_slave *slave) 215 { 216 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); 217 218 debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs); 219 220 qslave->dc = 0; 221 if (qslave->mode & SPI_CPHA) 222 qslave->dc |= QSPI_CKPHA(slave->cs); 223 if (qslave->mode & SPI_CPOL) 224 qslave->dc |= QSPI_CKPOL(slave->cs); 225 if (qslave->mode & SPI_CS_HIGH) 226 qslave->dc |= QSPI_CSPOL(slave->cs); 227 228 writel(qslave->dc, &qslave->base->dc); 229 writel(0, &qslave->base->cmd); 230 writel(0, &qslave->base->data); 231 232 return 0; 233 } 234 235 void spi_release_bus(struct spi_slave *slave) 236 { 237 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); 238 239 debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs); 240 241 writel(0, &qslave->base->dc); 242 writel(0, &qslave->base->cmd); 243 writel(0, &qslave->base->data); 244 } 245 246 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 247 void *din, unsigned long flags) 248 { 249 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); 250 uint words = bitlen >> 3; /* fixed 8-bit word length */ 251 const uchar *txp = dout; 252 uchar *rxp = din; 253 uint status; 254 int timeout; 255 256 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) 257 int val; 258 #endif 259 260 debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", 261 slave->bus, slave->cs, bitlen, words, flags); 262 263 /* Setup mmap flags */ 264 if (flags & SPI_XFER_MMAP) { 265 writel(MM_SWITCH, &qslave->base->memswitch); 266 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) 267 val = readl(CORE_CTRL_IO); 268 val |= MEM_CS; 269 writel(val, CORE_CTRL_IO); 270 #endif 271 return 0; 272 } else if (flags & SPI_XFER_MMAP_END) { 273 writel(~MM_SWITCH, &qslave->base->memswitch); 274 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) 275 val = readl(CORE_CTRL_IO); 276 val &= MEM_CS_UNSELECT; 277 writel(val, CORE_CTRL_IO); 278 #endif 279 return 0; 280 } 281 282 if (bitlen == 0) 283 return -1; 284 285 if (bitlen % 8) { 286 debug("spi_xfer: Non byte aligned SPI transfer\n"); 287 return -1; 288 } 289 290 /* Setup command reg */ 291 qslave->cmd = 0; 292 qslave->cmd |= QSPI_WLEN(8); 293 qslave->cmd |= QSPI_EN_CS(slave->cs); 294 if (flags & SPI_3WIRE) 295 qslave->cmd |= QSPI_3_PIN; 296 qslave->cmd |= 0xfff; 297 298 /* FIXME: This delay is required for successfull 299 * completion of read/write/erase. Once its root 300 * caused, it will be remove from the driver. 301 */ 302 #ifdef CONFIG_AM43XX 303 udelay(100); 304 #endif 305 while (words--) { 306 if (txp) { 307 debug("tx cmd %08x dc %08x data %02x\n", 308 qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp); 309 writel(*txp++, &qslave->base->data); 310 writel(qslave->cmd | QSPI_WR_SNGL, 311 &qslave->base->cmd); 312 status = readl(&qslave->base->status); 313 timeout = QSPI_TIMEOUT; 314 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { 315 if (--timeout < 0) { 316 printf("spi_xfer: TX timeout!\n"); 317 return -1; 318 } 319 status = readl(&qslave->base->status); 320 } 321 debug("tx done, status %08x\n", status); 322 } 323 if (rxp) { 324 qslave->cmd |= QSPI_RD_SNGL; 325 debug("rx cmd %08x dc %08x\n", 326 qslave->cmd, qslave->dc); 327 #ifdef CONFIG_DRA7XX 328 udelay(500); 329 #endif 330 writel(qslave->cmd, &qslave->base->cmd); 331 status = readl(&qslave->base->status); 332 timeout = QSPI_TIMEOUT; 333 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { 334 if (--timeout < 0) { 335 printf("spi_xfer: RX timeout!\n"); 336 return -1; 337 } 338 status = readl(&qslave->base->status); 339 } 340 *rxp++ = readl(&qslave->base->data); 341 debug("rx done, status %08x, read %02x\n", 342 status, *(rxp-1)); 343 } 344 } 345 346 /* Terminate frame */ 347 if (flags & SPI_XFER_END) 348 spi_cs_deactivate(slave); 349 350 return 0; 351 } 352 353 /* TODO: control from sf layer to here through dm-spi */ 354 #ifdef CONFIG_TI_EDMA3 355 void spi_flash_copy_mmap(void *data, void *offset, size_t len) 356 { 357 unsigned int addr = (unsigned int) (data); 358 unsigned int edma_slot_num = 1; 359 360 /* Invalidate the area, so no writeback into the RAM races with DMA */ 361 invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN)); 362 363 /* enable edma3 clocks */ 364 enable_edma3_clocks(); 365 366 /* Call edma3 api to do actual DMA transfer */ 367 edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len); 368 369 /* disable edma3 clocks */ 370 disable_edma3_clocks(); 371 372 *((unsigned int *)offset) += len; 373 } 374 #endif 375