1 /* 2 * NVIDIA Tegra210 QSPI controller driver 3 * 4 * (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch-tegra/clk_rst.h> 14 #include <spi.h> 15 #include <fdtdec.h> 16 #include "tegra_spi.h" 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 /* COMMAND1 */ 21 #define QSPI_CMD1_GO BIT(31) 22 #define QSPI_CMD1_M_S BIT(30) 23 #define QSPI_CMD1_MODE_MASK GENMASK(1,0) 24 #define QSPI_CMD1_MODE_SHIFT 28 25 #define QSPI_CMD1_CS_SEL_MASK GENMASK(1,0) 26 #define QSPI_CMD1_CS_SEL_SHIFT 26 27 #define QSPI_CMD1_CS_POL_INACTIVE0 BIT(22) 28 #define QSPI_CMD1_CS_SW_HW BIT(21) 29 #define QSPI_CMD1_CS_SW_VAL BIT(20) 30 #define QSPI_CMD1_IDLE_SDA_MASK GENMASK(1,0) 31 #define QSPI_CMD1_IDLE_SDA_SHIFT 18 32 #define QSPI_CMD1_BIDIR BIT(17) 33 #define QSPI_CMD1_LSBI_FE BIT(16) 34 #define QSPI_CMD1_LSBY_FE BIT(15) 35 #define QSPI_CMD1_BOTH_EN_BIT BIT(14) 36 #define QSPI_CMD1_BOTH_EN_BYTE BIT(13) 37 #define QSPI_CMD1_RX_EN BIT(12) 38 #define QSPI_CMD1_TX_EN BIT(11) 39 #define QSPI_CMD1_PACKED BIT(5) 40 #define QSPI_CMD1_BITLEN_MASK GENMASK(4,0) 41 #define QSPI_CMD1_BITLEN_SHIFT 0 42 43 /* COMMAND2 */ 44 #define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6) 45 #define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6) 46 #define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0) 47 #define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0) 48 49 /* TRANSFER STATUS */ 50 #define QSPI_XFER_STS_RDY BIT(30) 51 52 /* FIFO STATUS */ 53 #define QSPI_FIFO_STS_CS_INACTIVE BIT(31) 54 #define QSPI_FIFO_STS_FRAME_END BIT(30) 55 #define QSPI_FIFO_STS_RX_FIFO_FLUSH BIT(15) 56 #define QSPI_FIFO_STS_TX_FIFO_FLUSH BIT(14) 57 #define QSPI_FIFO_STS_ERR BIT(8) 58 #define QSPI_FIFO_STS_TX_FIFO_OVF BIT(7) 59 #define QSPI_FIFO_STS_TX_FIFO_UNR BIT(6) 60 #define QSPI_FIFO_STS_RX_FIFO_OVF BIT(5) 61 #define QSPI_FIFO_STS_RX_FIFO_UNR BIT(4) 62 #define QSPI_FIFO_STS_TX_FIFO_FULL BIT(3) 63 #define QSPI_FIFO_STS_TX_FIFO_EMPTY BIT(2) 64 #define QSPI_FIFO_STS_RX_FIFO_FULL BIT(1) 65 #define QSPI_FIFO_STS_RX_FIFO_EMPTY BIT(0) 66 67 #define QSPI_TIMEOUT 1000 68 69 struct qspi_regs { 70 u32 command1; /* 000:QSPI_COMMAND1 register */ 71 u32 command2; /* 004:QSPI_COMMAND2 register */ 72 u32 timing1; /* 008:QSPI_CS_TIM1 register */ 73 u32 timing2; /* 00c:QSPI_CS_TIM2 register */ 74 u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */ 75 u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */ 76 u32 tx_data; /* 018:QSPI_TX_DATA register */ 77 u32 rx_data; /* 01c:QSPI_RX_DATA register */ 78 u32 dma_ctl; /* 020:QSPI_DMA_CTL register */ 79 u32 dma_blk; /* 024:QSPI_DMA_BLK register */ 80 u32 rsvd[56]; /* 028-107 reserved */ 81 u32 tx_fifo; /* 108:QSPI_FIFO1 register */ 82 u32 rsvd2[31]; /* 10c-187 reserved */ 83 u32 rx_fifo; /* 188:QSPI_FIFO2 register */ 84 u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */ 85 }; 86 87 struct tegra210_qspi_priv { 88 struct qspi_regs *regs; 89 unsigned int freq; 90 unsigned int mode; 91 int periph_id; 92 int valid; 93 int last_transaction_us; 94 }; 95 96 static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) 97 { 98 struct tegra_spi_platdata *plat = bus->platdata; 99 const void *blob = gd->fdt_blob; 100 int node = bus->of_offset; 101 102 plat->base = dev_get_addr(bus); 103 plat->periph_id = clock_decode_periph_id(blob, node); 104 105 if (plat->periph_id == PERIPH_ID_NONE) { 106 debug("%s: could not decode periph id %d\n", __func__, 107 plat->periph_id); 108 return -FDT_ERR_NOTFOUND; 109 } 110 111 /* Use 500KHz as a suitable default */ 112 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 113 500000); 114 plat->deactivate_delay_us = fdtdec_get_int(blob, node, 115 "spi-deactivate-delay", 0); 116 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", 117 __func__, plat->base, plat->periph_id, plat->frequency, 118 plat->deactivate_delay_us); 119 120 return 0; 121 } 122 123 static int tegra210_qspi_probe(struct udevice *bus) 124 { 125 struct tegra_spi_platdata *plat = dev_get_platdata(bus); 126 struct tegra210_qspi_priv *priv = dev_get_priv(bus); 127 128 priv->regs = (struct qspi_regs *)plat->base; 129 130 priv->last_transaction_us = timer_get_us(); 131 priv->freq = plat->frequency; 132 priv->periph_id = plat->periph_id; 133 134 return 0; 135 } 136 137 static int tegra210_qspi_claim_bus(struct udevice *bus) 138 { 139 struct tegra210_qspi_priv *priv = dev_get_priv(bus); 140 struct qspi_regs *regs = priv->regs; 141 142 /* Change SPI clock to correct frequency, PLLP_OUT0 source */ 143 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); 144 145 debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); 146 147 /* Set master mode and sw controlled CS */ 148 setbits_le32(®s->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW | 149 (priv->mode << QSPI_CMD1_MODE_SHIFT)); 150 debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); 151 152 return 0; 153 } 154 155 /** 156 * Activate the CS by driving it LOW 157 * 158 * @param slave Pointer to spi_slave to which controller has to 159 * communicate with 160 */ 161 static void spi_cs_activate(struct udevice *dev) 162 { 163 struct udevice *bus = dev->parent; 164 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 165 struct tegra210_qspi_priv *priv = dev_get_priv(bus); 166 167 /* If it's too soon to do another transaction, wait */ 168 if (pdata->deactivate_delay_us && 169 priv->last_transaction_us) { 170 ulong delay_us; /* The delay completed so far */ 171 delay_us = timer_get_us() - priv->last_transaction_us; 172 if (delay_us < pdata->deactivate_delay_us) 173 udelay(pdata->deactivate_delay_us - delay_us); 174 } 175 176 clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); 177 } 178 179 /** 180 * Deactivate the CS by driving it HIGH 181 * 182 * @param slave Pointer to spi_slave to which controller has to 183 * communicate with 184 */ 185 static void spi_cs_deactivate(struct udevice *dev) 186 { 187 struct udevice *bus = dev->parent; 188 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 189 struct tegra210_qspi_priv *priv = dev_get_priv(bus); 190 191 setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); 192 193 /* Remember time of this transaction so we can honour the bus delay */ 194 if (pdata->deactivate_delay_us) 195 priv->last_transaction_us = timer_get_us(); 196 197 debug("Deactivate CS, bus '%s'\n", bus->name); 198 } 199 200 static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen, 201 const void *data_out, void *data_in, 202 unsigned long flags) 203 { 204 struct udevice *bus = dev->parent; 205 struct tegra210_qspi_priv *priv = dev_get_priv(bus); 206 struct qspi_regs *regs = priv->regs; 207 u32 reg, tmpdout, tmpdin = 0; 208 const u8 *dout = data_out; 209 u8 *din = data_in; 210 int num_bytes, tm, ret; 211 212 debug("%s: slave %u:%u dout %p din %p bitlen %u\n", 213 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); 214 if (bitlen % 8) 215 return -1; 216 num_bytes = bitlen / 8; 217 218 ret = 0; 219 220 /* clear all error status bits */ 221 reg = readl(®s->fifo_status); 222 writel(reg, ®s->fifo_status); 223 224 /* flush RX/TX FIFOs */ 225 setbits_le32(®s->fifo_status, 226 (QSPI_FIFO_STS_RX_FIFO_FLUSH | 227 QSPI_FIFO_STS_TX_FIFO_FLUSH)); 228 229 tm = QSPI_TIMEOUT; 230 while ((tm && readl(®s->fifo_status) & 231 (QSPI_FIFO_STS_RX_FIFO_FLUSH | 232 QSPI_FIFO_STS_TX_FIFO_FLUSH))) { 233 tm--; 234 udelay(1); 235 } 236 237 if (!tm) { 238 printf("%s: timeout during QSPI FIFO flush!\n", 239 __func__); 240 return -1; 241 } 242 243 /* 244 * Notes: 245 * 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs; 246 * 2. don't set RX_EN and TX_EN yet. 247 * (SW needs to make sure that while programming the blk_size, 248 * tx_en and rx_en bits must be zero) 249 * [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set 250 * i.e., both dout and din are not NULL. 251 */ 252 clrsetbits_le32(®s->command1, 253 (QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE | 254 QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN), 255 (spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT)); 256 257 /* set xfer size to 1 block (32 bits) */ 258 writel(0, ®s->dma_blk); 259 260 if (flags & SPI_XFER_BEGIN) 261 spi_cs_activate(dev); 262 263 /* handle data in 32-bit chunks */ 264 while (num_bytes > 0) { 265 int bytes; 266 267 tmpdout = 0; 268 bytes = (num_bytes > 4) ? 4 : num_bytes; 269 270 if (dout != NULL) { 271 memcpy((void *)&tmpdout, (void *)dout, bytes); 272 dout += bytes; 273 num_bytes -= bytes; 274 writel(tmpdout, ®s->tx_fifo); 275 setbits_le32(®s->command1, QSPI_CMD1_TX_EN); 276 } 277 278 if (din != NULL) 279 setbits_le32(®s->command1, QSPI_CMD1_RX_EN); 280 281 /* clear ready bit */ 282 setbits_le32(®s->xfer_status, QSPI_XFER_STS_RDY); 283 284 clrsetbits_le32(®s->command1, 285 QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT, 286 (bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT); 287 288 /* Need to stabilize other reg bits before GO bit set. 289 * As per the TRM: 290 * "For successful operation at various freq combinations, 291 * a minimum of 4-5 spi_clk cycle delay might be required 292 * before enabling the PIO or DMA bits. The worst case delay 293 * calculation can be done considering slowest qspi_clk as 294 * 1MHz. Based on that 1us delay should be enough before 295 * enabling PIO or DMA." Padded another 1us for safety. 296 */ 297 udelay(2); 298 setbits_le32(®s->command1, QSPI_CMD1_GO); 299 udelay(1); 300 301 /* 302 * Wait for SPI transmit FIFO to empty, or to time out. 303 * The RX FIFO status will be read and cleared last 304 */ 305 for (tm = 0; tm < QSPI_TIMEOUT; ++tm) { 306 u32 fifo_status, xfer_status; 307 308 xfer_status = readl(®s->xfer_status); 309 if (!(xfer_status & QSPI_XFER_STS_RDY)) 310 continue; 311 312 fifo_status = readl(®s->fifo_status); 313 if (fifo_status & QSPI_FIFO_STS_ERR) { 314 debug("%s: got a fifo error: ", __func__); 315 if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF) 316 debug("tx FIFO overflow "); 317 if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR) 318 debug("tx FIFO underrun "); 319 if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF) 320 debug("rx FIFO overflow "); 321 if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR) 322 debug("rx FIFO underrun "); 323 if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL) 324 debug("tx FIFO full "); 325 if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY) 326 debug("tx FIFO empty "); 327 if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL) 328 debug("rx FIFO full "); 329 if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY) 330 debug("rx FIFO empty "); 331 debug("\n"); 332 break; 333 } 334 335 if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) { 336 tmpdin = readl(®s->rx_fifo); 337 if (din != NULL) { 338 memcpy(din, &tmpdin, bytes); 339 din += bytes; 340 num_bytes -= bytes; 341 } 342 } 343 break; 344 } 345 346 if (tm >= QSPI_TIMEOUT) 347 ret = tm; 348 349 /* clear ACK RDY, etc. bits */ 350 writel(readl(®s->fifo_status), ®s->fifo_status); 351 } 352 353 if (flags & SPI_XFER_END) 354 spi_cs_deactivate(dev); 355 356 debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", 357 __func__, tmpdin, readl(®s->fifo_status)); 358 359 if (ret) { 360 printf("%s: timeout during SPI transfer, tm %d\n", 361 __func__, ret); 362 return -1; 363 } 364 365 return ret; 366 } 367 368 static int tegra210_qspi_set_speed(struct udevice *bus, uint speed) 369 { 370 struct tegra_spi_platdata *plat = bus->platdata; 371 struct tegra210_qspi_priv *priv = dev_get_priv(bus); 372 373 if (speed > plat->frequency) 374 speed = plat->frequency; 375 priv->freq = speed; 376 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); 377 378 return 0; 379 } 380 381 static int tegra210_qspi_set_mode(struct udevice *bus, uint mode) 382 { 383 struct tegra210_qspi_priv *priv = dev_get_priv(bus); 384 385 priv->mode = mode; 386 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); 387 388 return 0; 389 } 390 391 static const struct dm_spi_ops tegra210_qspi_ops = { 392 .claim_bus = tegra210_qspi_claim_bus, 393 .xfer = tegra210_qspi_xfer, 394 .set_speed = tegra210_qspi_set_speed, 395 .set_mode = tegra210_qspi_set_mode, 396 /* 397 * cs_info is not needed, since we require all chip selects to be 398 * in the device tree explicitly 399 */ 400 }; 401 402 static const struct udevice_id tegra210_qspi_ids[] = { 403 { .compatible = "nvidia,tegra210-qspi" }, 404 { } 405 }; 406 407 U_BOOT_DRIVER(tegra210_qspi) = { 408 .name = "tegra210-qspi", 409 .id = UCLASS_SPI, 410 .of_match = tegra210_qspi_ids, 411 .ops = &tegra210_qspi_ops, 412 .ofdata_to_platdata = tegra210_qspi_ofdata_to_platdata, 413 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), 414 .priv_auto_alloc_size = sizeof(struct tegra210_qspi_priv), 415 .per_child_auto_alloc_size = sizeof(struct spi_slave), 416 .probe = tegra210_qspi_probe, 417 }; 418