1 /* 2 * NVIDIA Tegra SPI-SLINK controller 3 * 4 * Copyright (c) 2010-2013 NVIDIA Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch-tegra/clk_rst.h> 14 #include <spi.h> 15 #include <fdtdec.h> 16 #include "tegra_spi.h" 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 /* COMMAND */ 21 #define SLINK_CMD_ENB BIT(31) 22 #define SLINK_CMD_GO BIT(30) 23 #define SLINK_CMD_M_S BIT(28) 24 #define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24) 25 #define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH BIT(24) 26 #define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24) 27 #define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24) 28 #define SLINK_CMD_IDLE_SCLK_MASK (3 << 24) 29 #define SLINK_CMD_CK_SDA BIT(21) 30 #define SLINK_CMD_CS_POL BIT(13) 31 #define SLINK_CMD_CS_VAL BIT(12) 32 #define SLINK_CMD_CS_SOFT BIT(11) 33 #define SLINK_CMD_BIT_LENGTH BIT(4) 34 #define SLINK_CMD_BIT_LENGTH_MASK GENMASK(4, 0) 35 /* COMMAND2 */ 36 #define SLINK_CMD2_TXEN BIT(30) 37 #define SLINK_CMD2_RXEN BIT(31) 38 #define SLINK_CMD2_SS_EN BIT(18) 39 #define SLINK_CMD2_SS_EN_SHIFT 18 40 #define SLINK_CMD2_SS_EN_MASK GENMASK(19, 18) 41 #define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17) 42 /* STATUS */ 43 #define SLINK_STAT_BSY BIT(31) 44 #define SLINK_STAT_RDY BIT(30) 45 #define SLINK_STAT_ERR BIT(29) 46 #define SLINK_STAT_RXF_FLUSH BIT(27) 47 #define SLINK_STAT_TXF_FLUSH BIT(26) 48 #define SLINK_STAT_RXF_OVF BIT(25) 49 #define SLINK_STAT_TXF_UNR BIT(24) 50 #define SLINK_STAT_RXF_EMPTY BIT(23) 51 #define SLINK_STAT_RXF_FULL BIT(22) 52 #define SLINK_STAT_TXF_EMPTY BIT(21) 53 #define SLINK_STAT_TXF_FULL BIT(20) 54 #define SLINK_STAT_TXF_OVF BIT(19) 55 #define SLINK_STAT_RXF_UNR BIT(18) 56 #define SLINK_STAT_CUR_BLKCNT BIT(15) 57 /* STATUS2 */ 58 #define SLINK_STAT2_RXF_FULL_CNT BIT(16) 59 #define SLINK_STAT2_TXF_FULL_CNT BIT(0) 60 61 #define SPI_TIMEOUT 1000 62 #define TEGRA_SPI_MAX_FREQ 52000000 63 64 struct spi_regs { 65 u32 command; /* SLINK_COMMAND_0 register */ 66 u32 command2; /* SLINK_COMMAND2_0 reg */ 67 u32 status; /* SLINK_STATUS_0 register */ 68 u32 reserved; /* Reserved offset 0C */ 69 u32 mas_data; /* SLINK_MAS_DATA_0 reg */ 70 u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */ 71 u32 dma_ctl; /* SLINK_DMA_CTL_0 register */ 72 u32 status2; /* SLINK_STATUS2_0 reg */ 73 u32 rsvd[56]; /* 0x20 to 0xFF reserved */ 74 u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */ 75 u32 rsvd2[31]; /* 0x104 to 0x17F reserved */ 76 u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */ 77 }; 78 79 struct tegra30_spi_priv { 80 struct spi_regs *regs; 81 unsigned int freq; 82 unsigned int mode; 83 int periph_id; 84 int valid; 85 int last_transaction_us; 86 }; 87 88 struct tegra_spi_slave { 89 struct spi_slave slave; 90 struct tegra30_spi_priv *ctrl; 91 }; 92 93 static int tegra30_spi_ofdata_to_platdata(struct udevice *bus) 94 { 95 struct tegra_spi_platdata *plat = bus->platdata; 96 const void *blob = gd->fdt_blob; 97 int node = bus->of_offset; 98 99 plat->base = dev_get_addr(bus); 100 plat->periph_id = clock_decode_periph_id(blob, node); 101 102 if (plat->periph_id == PERIPH_ID_NONE) { 103 debug("%s: could not decode periph id %d\n", __func__, 104 plat->periph_id); 105 return -FDT_ERR_NOTFOUND; 106 } 107 108 /* Use 500KHz as a suitable default */ 109 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 110 500000); 111 plat->deactivate_delay_us = fdtdec_get_int(blob, node, 112 "spi-deactivate-delay", 0); 113 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", 114 __func__, plat->base, plat->periph_id, plat->frequency, 115 plat->deactivate_delay_us); 116 117 return 0; 118 } 119 120 static int tegra30_spi_probe(struct udevice *bus) 121 { 122 struct tegra_spi_platdata *plat = dev_get_platdata(bus); 123 struct tegra30_spi_priv *priv = dev_get_priv(bus); 124 125 priv->regs = (struct spi_regs *)plat->base; 126 127 priv->last_transaction_us = timer_get_us(); 128 priv->freq = plat->frequency; 129 priv->periph_id = plat->periph_id; 130 131 return 0; 132 } 133 134 static int tegra30_spi_claim_bus(struct udevice *dev) 135 { 136 struct udevice *bus = dev->parent; 137 struct tegra30_spi_priv *priv = dev_get_priv(bus); 138 struct spi_regs *regs = priv->regs; 139 u32 reg; 140 141 /* Change SPI clock to correct frequency, PLLP_OUT0 source */ 142 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, 143 priv->freq); 144 145 /* Clear stale status here */ 146 reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \ 147 SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF; 148 writel(reg, ®s->status); 149 debug("%s: STATUS = %08x\n", __func__, readl(®s->status)); 150 151 /* Set master mode and sw controlled CS */ 152 reg = readl(®s->command); 153 reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT; 154 writel(reg, ®s->command); 155 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command)); 156 157 return 0; 158 } 159 160 static void spi_cs_activate(struct udevice *dev) 161 { 162 struct udevice *bus = dev->parent; 163 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 164 struct tegra30_spi_priv *priv = dev_get_priv(bus); 165 166 /* If it's too soon to do another transaction, wait */ 167 if (pdata->deactivate_delay_us && 168 priv->last_transaction_us) { 169 ulong delay_us; /* The delay completed so far */ 170 delay_us = timer_get_us() - priv->last_transaction_us; 171 if (delay_us < pdata->deactivate_delay_us) 172 udelay(pdata->deactivate_delay_us - delay_us); 173 } 174 175 /* CS is negated on Tegra, so drive a 1 to get a 0 */ 176 setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL); 177 } 178 179 static void spi_cs_deactivate(struct udevice *dev) 180 { 181 struct udevice *bus = dev->parent; 182 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 183 struct tegra30_spi_priv *priv = dev_get_priv(bus); 184 185 /* CS is negated on Tegra, so drive a 0 to get a 1 */ 186 clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL); 187 188 /* Remember time of this transaction so we can honour the bus delay */ 189 if (pdata->deactivate_delay_us) 190 priv->last_transaction_us = timer_get_us(); 191 } 192 193 static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen, 194 const void *data_out, void *data_in, 195 unsigned long flags) 196 { 197 struct udevice *bus = dev->parent; 198 struct tegra30_spi_priv *priv = dev_get_priv(bus); 199 struct spi_regs *regs = priv->regs; 200 u32 reg, tmpdout, tmpdin = 0; 201 const u8 *dout = data_out; 202 u8 *din = data_in; 203 int num_bytes; 204 int ret; 205 206 debug("%s: slave %u:%u dout %p din %p bitlen %u\n", 207 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); 208 if (bitlen % 8) 209 return -1; 210 num_bytes = bitlen / 8; 211 212 ret = 0; 213 214 reg = readl(®s->status); 215 writel(reg, ®s->status); /* Clear all SPI events via R/W */ 216 debug("%s entry: STATUS = %08x\n", __func__, reg); 217 218 reg = readl(®s->status2); 219 writel(reg, ®s->status2); /* Clear all STATUS2 events via R/W */ 220 debug("%s entry: STATUS2 = %08x\n", __func__, reg); 221 222 debug("%s entry: COMMAND = %08x\n", __func__, readl(®s->command)); 223 224 clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK, 225 SLINK_CMD2_TXEN | SLINK_CMD2_RXEN | 226 (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT)); 227 debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2)); 228 229 if (flags & SPI_XFER_BEGIN) 230 spi_cs_activate(dev); 231 232 /* handle data in 32-bit chunks */ 233 while (num_bytes > 0) { 234 int bytes; 235 int is_read = 0; 236 int tm, i; 237 238 tmpdout = 0; 239 bytes = (num_bytes > 4) ? 4 : num_bytes; 240 241 if (dout != NULL) { 242 for (i = 0; i < bytes; ++i) 243 tmpdout = (tmpdout << 8) | dout[i]; 244 dout += bytes; 245 } 246 247 num_bytes -= bytes; 248 249 clrsetbits_le32(®s->command, SLINK_CMD_BIT_LENGTH_MASK, 250 bytes * 8 - 1); 251 writel(tmpdout, ®s->tx_fifo); 252 setbits_le32(®s->command, SLINK_CMD_GO); 253 254 /* 255 * Wait for SPI transmit FIFO to empty, or to time out. 256 * The RX FIFO status will be read and cleared last 257 */ 258 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { 259 u32 status; 260 261 status = readl(®s->status); 262 263 /* We can exit when we've had both RX and TX activity */ 264 if (is_read && (status & SLINK_STAT_TXF_EMPTY)) 265 break; 266 267 if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) != 268 SLINK_STAT_RDY) 269 tm++; 270 271 else if (!(status & SLINK_STAT_RXF_EMPTY)) { 272 tmpdin = readl(®s->rx_fifo); 273 is_read = 1; 274 275 /* swap bytes read in */ 276 if (din != NULL) { 277 for (i = bytes - 1; i >= 0; --i) { 278 din[i] = tmpdin & 0xff; 279 tmpdin >>= 8; 280 } 281 din += bytes; 282 } 283 } 284 } 285 286 if (tm >= SPI_TIMEOUT) 287 ret = tm; 288 289 /* clear ACK RDY, etc. bits */ 290 writel(readl(®s->status), ®s->status); 291 } 292 293 if (flags & SPI_XFER_END) 294 spi_cs_deactivate(dev); 295 296 debug("%s: transfer ended. Value=%08x, status = %08x\n", 297 __func__, tmpdin, readl(®s->status)); 298 299 if (ret) { 300 printf("%s: timeout during SPI transfer, tm %d\n", 301 __func__, ret); 302 return -1; 303 } 304 305 return 0; 306 } 307 308 static int tegra30_spi_set_speed(struct udevice *bus, uint speed) 309 { 310 struct tegra_spi_platdata *plat = bus->platdata; 311 struct tegra30_spi_priv *priv = dev_get_priv(bus); 312 313 if (speed > plat->frequency) 314 speed = plat->frequency; 315 priv->freq = speed; 316 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); 317 318 return 0; 319 } 320 321 static int tegra30_spi_set_mode(struct udevice *bus, uint mode) 322 { 323 struct tegra30_spi_priv *priv = dev_get_priv(bus); 324 struct spi_regs *regs = priv->regs; 325 u32 reg; 326 327 reg = readl(®s->command); 328 329 /* Set CPOL and CPHA */ 330 reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA); 331 if (mode & SPI_CPHA) 332 reg |= SLINK_CMD_CK_SDA; 333 334 if (mode & SPI_CPOL) 335 reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH; 336 else 337 reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW; 338 339 writel(reg, ®s->command); 340 341 priv->mode = mode; 342 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); 343 344 return 0; 345 } 346 347 static const struct dm_spi_ops tegra30_spi_ops = { 348 .claim_bus = tegra30_spi_claim_bus, 349 .xfer = tegra30_spi_xfer, 350 .set_speed = tegra30_spi_set_speed, 351 .set_mode = tegra30_spi_set_mode, 352 /* 353 * cs_info is not needed, since we require all chip selects to be 354 * in the device tree explicitly 355 */ 356 }; 357 358 static const struct udevice_id tegra30_spi_ids[] = { 359 { .compatible = "nvidia,tegra20-slink" }, 360 { } 361 }; 362 363 U_BOOT_DRIVER(tegra30_spi) = { 364 .name = "tegra20_slink", 365 .id = UCLASS_SPI, 366 .of_match = tegra30_spi_ids, 367 .ops = &tegra30_spi_ops, 368 .ofdata_to_platdata = tegra30_spi_ofdata_to_platdata, 369 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), 370 .priv_auto_alloc_size = sizeof(struct tegra30_spi_priv), 371 .probe = tegra30_spi_probe, 372 }; 373