1 /* 2 * NVIDIA Tegra SPI-SLINK controller 3 * 4 * Copyright (c) 2010-2013 NVIDIA Corporation 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <dm.h> 26 #include <asm/io.h> 27 #include <asm/arch/clock.h> 28 #include <asm/arch-tegra/clk_rst.h> 29 #include <spi.h> 30 #include <fdtdec.h> 31 #include "tegra_spi.h" 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 /* COMMAND */ 36 #define SLINK_CMD_ENB BIT(31) 37 #define SLINK_CMD_GO BIT(30) 38 #define SLINK_CMD_M_S BIT(28) 39 #define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24) 40 #define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH BIT(24) 41 #define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24) 42 #define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24) 43 #define SLINK_CMD_IDLE_SCLK_MASK (3 << 24) 44 #define SLINK_CMD_CK_SDA BIT(21) 45 #define SLINK_CMD_CS_POL BIT(13) 46 #define SLINK_CMD_CS_VAL BIT(12) 47 #define SLINK_CMD_CS_SOFT BIT(11) 48 #define SLINK_CMD_BIT_LENGTH BIT(4) 49 #define SLINK_CMD_BIT_LENGTH_MASK GENMASK(4, 0) 50 /* COMMAND2 */ 51 #define SLINK_CMD2_TXEN BIT(30) 52 #define SLINK_CMD2_RXEN BIT(31) 53 #define SLINK_CMD2_SS_EN BIT(18) 54 #define SLINK_CMD2_SS_EN_SHIFT 18 55 #define SLINK_CMD2_SS_EN_MASK GENMASK(19, 18) 56 #define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17) 57 /* STATUS */ 58 #define SLINK_STAT_BSY BIT(31) 59 #define SLINK_STAT_RDY BIT(30) 60 #define SLINK_STAT_ERR BIT(29) 61 #define SLINK_STAT_RXF_FLUSH BIT(27) 62 #define SLINK_STAT_TXF_FLUSH BIT(26) 63 #define SLINK_STAT_RXF_OVF BIT(25) 64 #define SLINK_STAT_TXF_UNR BIT(24) 65 #define SLINK_STAT_RXF_EMPTY BIT(23) 66 #define SLINK_STAT_RXF_FULL BIT(22) 67 #define SLINK_STAT_TXF_EMPTY BIT(21) 68 #define SLINK_STAT_TXF_FULL BIT(20) 69 #define SLINK_STAT_TXF_OVF BIT(19) 70 #define SLINK_STAT_RXF_UNR BIT(18) 71 #define SLINK_STAT_CUR_BLKCNT BIT(15) 72 /* STATUS2 */ 73 #define SLINK_STAT2_RXF_FULL_CNT BIT(16) 74 #define SLINK_STAT2_TXF_FULL_CNT BIT(0) 75 76 #define SPI_TIMEOUT 1000 77 #define TEGRA_SPI_MAX_FREQ 52000000 78 79 struct spi_regs { 80 u32 command; /* SLINK_COMMAND_0 register */ 81 u32 command2; /* SLINK_COMMAND2_0 reg */ 82 u32 status; /* SLINK_STATUS_0 register */ 83 u32 reserved; /* Reserved offset 0C */ 84 u32 mas_data; /* SLINK_MAS_DATA_0 reg */ 85 u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */ 86 u32 dma_ctl; /* SLINK_DMA_CTL_0 register */ 87 u32 status2; /* SLINK_STATUS2_0 reg */ 88 u32 rsvd[56]; /* 0x20 to 0xFF reserved */ 89 u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */ 90 u32 rsvd2[31]; /* 0x104 to 0x17F reserved */ 91 u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */ 92 }; 93 94 struct tegra30_spi_priv { 95 struct spi_regs *regs; 96 unsigned int freq; 97 unsigned int mode; 98 int periph_id; 99 int valid; 100 int last_transaction_us; 101 }; 102 103 struct tegra_spi_slave { 104 struct spi_slave slave; 105 struct tegra30_spi_priv *ctrl; 106 }; 107 108 static int tegra30_spi_ofdata_to_platdata(struct udevice *bus) 109 { 110 struct tegra_spi_platdata *plat = bus->platdata; 111 const void *blob = gd->fdt_blob; 112 int node = bus->of_offset; 113 114 plat->base = dev_get_addr(bus); 115 plat->periph_id = clock_decode_periph_id(blob, node); 116 117 if (plat->periph_id == PERIPH_ID_NONE) { 118 debug("%s: could not decode periph id %d\n", __func__, 119 plat->periph_id); 120 return -FDT_ERR_NOTFOUND; 121 } 122 123 /* Use 500KHz as a suitable default */ 124 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 125 500000); 126 plat->deactivate_delay_us = fdtdec_get_int(blob, node, 127 "spi-deactivate-delay", 0); 128 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", 129 __func__, plat->base, plat->periph_id, plat->frequency, 130 plat->deactivate_delay_us); 131 132 return 0; 133 } 134 135 static int tegra30_spi_probe(struct udevice *bus) 136 { 137 struct tegra_spi_platdata *plat = dev_get_platdata(bus); 138 struct tegra30_spi_priv *priv = dev_get_priv(bus); 139 140 priv->regs = (struct spi_regs *)plat->base; 141 142 priv->last_transaction_us = timer_get_us(); 143 priv->freq = plat->frequency; 144 priv->periph_id = plat->periph_id; 145 146 return 0; 147 } 148 149 static int tegra30_spi_claim_bus(struct udevice *dev) 150 { 151 struct udevice *bus = dev->parent; 152 struct tegra30_spi_priv *priv = dev_get_priv(bus); 153 struct spi_regs *regs = priv->regs; 154 u32 reg; 155 156 /* Change SPI clock to correct frequency, PLLP_OUT0 source */ 157 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, 158 priv->freq); 159 160 /* Clear stale status here */ 161 reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \ 162 SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF; 163 writel(reg, ®s->status); 164 debug("%s: STATUS = %08x\n", __func__, readl(®s->status)); 165 166 /* Set master mode and sw controlled CS */ 167 reg = readl(®s->command); 168 reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT; 169 writel(reg, ®s->command); 170 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command)); 171 172 return 0; 173 } 174 175 static void spi_cs_activate(struct udevice *dev) 176 { 177 struct udevice *bus = dev->parent; 178 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 179 struct tegra30_spi_priv *priv = dev_get_priv(bus); 180 181 /* If it's too soon to do another transaction, wait */ 182 if (pdata->deactivate_delay_us && 183 priv->last_transaction_us) { 184 ulong delay_us; /* The delay completed so far */ 185 delay_us = timer_get_us() - priv->last_transaction_us; 186 if (delay_us < pdata->deactivate_delay_us) 187 udelay(pdata->deactivate_delay_us - delay_us); 188 } 189 190 /* CS is negated on Tegra, so drive a 1 to get a 0 */ 191 setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL); 192 } 193 194 static void spi_cs_deactivate(struct udevice *dev) 195 { 196 struct udevice *bus = dev->parent; 197 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 198 struct tegra30_spi_priv *priv = dev_get_priv(bus); 199 200 /* CS is negated on Tegra, so drive a 0 to get a 1 */ 201 clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL); 202 203 /* Remember time of this transaction so we can honour the bus delay */ 204 if (pdata->deactivate_delay_us) 205 priv->last_transaction_us = timer_get_us(); 206 } 207 208 static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen, 209 const void *data_out, void *data_in, 210 unsigned long flags) 211 { 212 struct udevice *bus = dev->parent; 213 struct tegra30_spi_priv *priv = dev_get_priv(bus); 214 struct spi_regs *regs = priv->regs; 215 u32 reg, tmpdout, tmpdin = 0; 216 const u8 *dout = data_out; 217 u8 *din = data_in; 218 int num_bytes; 219 int ret; 220 221 debug("%s: slave %u:%u dout %p din %p bitlen %u\n", 222 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); 223 if (bitlen % 8) 224 return -1; 225 num_bytes = bitlen / 8; 226 227 ret = 0; 228 229 reg = readl(®s->status); 230 writel(reg, ®s->status); /* Clear all SPI events via R/W */ 231 debug("%s entry: STATUS = %08x\n", __func__, reg); 232 233 reg = readl(®s->status2); 234 writel(reg, ®s->status2); /* Clear all STATUS2 events via R/W */ 235 debug("%s entry: STATUS2 = %08x\n", __func__, reg); 236 237 debug("%s entry: COMMAND = %08x\n", __func__, readl(®s->command)); 238 239 clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK, 240 SLINK_CMD2_TXEN | SLINK_CMD2_RXEN | 241 (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT)); 242 debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2)); 243 244 if (flags & SPI_XFER_BEGIN) 245 spi_cs_activate(dev); 246 247 /* handle data in 32-bit chunks */ 248 while (num_bytes > 0) { 249 int bytes; 250 int is_read = 0; 251 int tm, i; 252 253 tmpdout = 0; 254 bytes = (num_bytes > 4) ? 4 : num_bytes; 255 256 if (dout != NULL) { 257 for (i = 0; i < bytes; ++i) 258 tmpdout = (tmpdout << 8) | dout[i]; 259 dout += bytes; 260 } 261 262 num_bytes -= bytes; 263 264 clrsetbits_le32(®s->command, SLINK_CMD_BIT_LENGTH_MASK, 265 bytes * 8 - 1); 266 writel(tmpdout, ®s->tx_fifo); 267 setbits_le32(®s->command, SLINK_CMD_GO); 268 269 /* 270 * Wait for SPI transmit FIFO to empty, or to time out. 271 * The RX FIFO status will be read and cleared last 272 */ 273 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { 274 u32 status; 275 276 status = readl(®s->status); 277 278 /* We can exit when we've had both RX and TX activity */ 279 if (is_read && (status & SLINK_STAT_TXF_EMPTY)) 280 break; 281 282 if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) != 283 SLINK_STAT_RDY) 284 tm++; 285 286 else if (!(status & SLINK_STAT_RXF_EMPTY)) { 287 tmpdin = readl(®s->rx_fifo); 288 is_read = 1; 289 290 /* swap bytes read in */ 291 if (din != NULL) { 292 for (i = bytes - 1; i >= 0; --i) { 293 din[i] = tmpdin & 0xff; 294 tmpdin >>= 8; 295 } 296 din += bytes; 297 } 298 } 299 } 300 301 if (tm >= SPI_TIMEOUT) 302 ret = tm; 303 304 /* clear ACK RDY, etc. bits */ 305 writel(readl(®s->status), ®s->status); 306 } 307 308 if (flags & SPI_XFER_END) 309 spi_cs_deactivate(dev); 310 311 debug("%s: transfer ended. Value=%08x, status = %08x\n", 312 __func__, tmpdin, readl(®s->status)); 313 314 if (ret) { 315 printf("%s: timeout during SPI transfer, tm %d\n", 316 __func__, ret); 317 return -1; 318 } 319 320 return 0; 321 } 322 323 static int tegra30_spi_set_speed(struct udevice *bus, uint speed) 324 { 325 struct tegra_spi_platdata *plat = bus->platdata; 326 struct tegra30_spi_priv *priv = dev_get_priv(bus); 327 328 if (speed > plat->frequency) 329 speed = plat->frequency; 330 priv->freq = speed; 331 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); 332 333 return 0; 334 } 335 336 static int tegra30_spi_set_mode(struct udevice *bus, uint mode) 337 { 338 struct tegra30_spi_priv *priv = dev_get_priv(bus); 339 struct spi_regs *regs = priv->regs; 340 u32 reg; 341 342 reg = readl(®s->command); 343 344 /* Set CPOL and CPHA */ 345 reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA); 346 if (mode & SPI_CPHA) 347 reg |= SLINK_CMD_CK_SDA; 348 349 if (mode & SPI_CPOL) 350 reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH; 351 else 352 reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW; 353 354 writel(reg, ®s->command); 355 356 priv->mode = mode; 357 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); 358 359 return 0; 360 } 361 362 static const struct dm_spi_ops tegra30_spi_ops = { 363 .claim_bus = tegra30_spi_claim_bus, 364 .xfer = tegra30_spi_xfer, 365 .set_speed = tegra30_spi_set_speed, 366 .set_mode = tegra30_spi_set_mode, 367 /* 368 * cs_info is not needed, since we require all chip selects to be 369 * in the device tree explicitly 370 */ 371 }; 372 373 static const struct udevice_id tegra30_spi_ids[] = { 374 { .compatible = "nvidia,tegra20-slink" }, 375 { } 376 }; 377 378 U_BOOT_DRIVER(tegra30_spi) = { 379 .name = "tegra20_slink", 380 .id = UCLASS_SPI, 381 .of_match = tegra30_spi_ids, 382 .ops = &tegra30_spi_ops, 383 .ofdata_to_platdata = tegra30_spi_ofdata_to_platdata, 384 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), 385 .priv_auto_alloc_size = sizeof(struct tegra30_spi_priv), 386 .probe = tegra30_spi_probe, 387 }; 388