1 /* 2 * NVIDIA Tegra SPI-SLINK controller 3 * 4 * Copyright (c) 2010-2013 NVIDIA Corporation 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <dm.h> 26 #include <asm/io.h> 27 #include <asm/arch/clock.h> 28 #include <asm/arch-tegra/clk_rst.h> 29 #include <spi.h> 30 #include <fdtdec.h> 31 #include "tegra_spi.h" 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 /* COMMAND */ 36 #define SLINK_CMD_ENB (1 << 31) 37 #define SLINK_CMD_GO (1 << 30) 38 #define SLINK_CMD_M_S (1 << 28) 39 #define SLINK_CMD_CK_SDA (1 << 21) 40 #define SLINK_CMD_CS_POL (1 << 13) 41 #define SLINK_CMD_CS_VAL (1 << 12) 42 #define SLINK_CMD_CS_SOFT (1 << 11) 43 #define SLINK_CMD_BIT_LENGTH (1 << 4) 44 #define SLINK_CMD_BIT_LENGTH_MASK 0x0000001F 45 /* COMMAND2 */ 46 #define SLINK_CMD2_TXEN (1 << 30) 47 #define SLINK_CMD2_RXEN (1 << 31) 48 #define SLINK_CMD2_SS_EN (1 << 18) 49 #define SLINK_CMD2_SS_EN_SHIFT 18 50 #define SLINK_CMD2_SS_EN_MASK 0x000C0000 51 #define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 << 17) 52 /* STATUS */ 53 #define SLINK_STAT_BSY (1 << 31) 54 #define SLINK_STAT_RDY (1 << 30) 55 #define SLINK_STAT_ERR (1 << 29) 56 #define SLINK_STAT_RXF_FLUSH (1 << 27) 57 #define SLINK_STAT_TXF_FLUSH (1 << 26) 58 #define SLINK_STAT_RXF_OVF (1 << 25) 59 #define SLINK_STAT_TXF_UNR (1 << 24) 60 #define SLINK_STAT_RXF_EMPTY (1 << 23) 61 #define SLINK_STAT_RXF_FULL (1 << 22) 62 #define SLINK_STAT_TXF_EMPTY (1 << 21) 63 #define SLINK_STAT_TXF_FULL (1 << 20) 64 #define SLINK_STAT_TXF_OVF (1 << 19) 65 #define SLINK_STAT_RXF_UNR (1 << 18) 66 #define SLINK_STAT_CUR_BLKCNT (1 << 15) 67 /* STATUS2 */ 68 #define SLINK_STAT2_RXF_FULL_CNT (1 << 16) 69 #define SLINK_STAT2_TXF_FULL_CNT (1 << 0) 70 71 #define SPI_TIMEOUT 1000 72 #define TEGRA_SPI_MAX_FREQ 52000000 73 74 struct spi_regs { 75 u32 command; /* SLINK_COMMAND_0 register */ 76 u32 command2; /* SLINK_COMMAND2_0 reg */ 77 u32 status; /* SLINK_STATUS_0 register */ 78 u32 reserved; /* Reserved offset 0C */ 79 u32 mas_data; /* SLINK_MAS_DATA_0 reg */ 80 u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */ 81 u32 dma_ctl; /* SLINK_DMA_CTL_0 register */ 82 u32 status2; /* SLINK_STATUS2_0 reg */ 83 u32 rsvd[56]; /* 0x20 to 0xFF reserved */ 84 u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */ 85 u32 rsvd2[31]; /* 0x104 to 0x17F reserved */ 86 u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */ 87 }; 88 89 struct tegra30_spi_priv { 90 struct spi_regs *regs; 91 unsigned int freq; 92 unsigned int mode; 93 int periph_id; 94 int valid; 95 int last_transaction_us; 96 }; 97 98 struct tegra_spi_slave { 99 struct spi_slave slave; 100 struct tegra30_spi_priv *ctrl; 101 }; 102 103 static int tegra30_spi_ofdata_to_platdata(struct udevice *bus) 104 { 105 struct tegra_spi_platdata *plat = bus->platdata; 106 const void *blob = gd->fdt_blob; 107 int node = bus->of_offset; 108 109 plat->base = fdtdec_get_addr(blob, node, "reg"); 110 plat->periph_id = clock_decode_periph_id(blob, node); 111 112 if (plat->periph_id == PERIPH_ID_NONE) { 113 debug("%s: could not decode periph id %d\n", __func__, 114 plat->periph_id); 115 return -FDT_ERR_NOTFOUND; 116 } 117 118 /* Use 500KHz as a suitable default */ 119 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 120 500000); 121 plat->deactivate_delay_us = fdtdec_get_int(blob, node, 122 "spi-deactivate-delay", 0); 123 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", 124 __func__, plat->base, plat->periph_id, plat->frequency, 125 plat->deactivate_delay_us); 126 127 return 0; 128 } 129 130 static int tegra30_spi_probe(struct udevice *bus) 131 { 132 struct tegra_spi_platdata *plat = dev_get_platdata(bus); 133 struct tegra30_spi_priv *priv = dev_get_priv(bus); 134 135 priv->regs = (struct spi_regs *)plat->base; 136 137 priv->last_transaction_us = timer_get_us(); 138 priv->freq = plat->frequency; 139 priv->periph_id = plat->periph_id; 140 141 return 0; 142 } 143 144 static int tegra30_spi_claim_bus(struct udevice *bus) 145 { 146 struct tegra30_spi_priv *priv = dev_get_priv(bus); 147 struct spi_regs *regs = priv->regs; 148 u32 reg; 149 150 /* Change SPI clock to correct frequency, PLLP_OUT0 source */ 151 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, 152 priv->freq); 153 154 /* Clear stale status here */ 155 reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \ 156 SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF; 157 writel(reg, ®s->status); 158 debug("%s: STATUS = %08x\n", __func__, readl(®s->status)); 159 160 /* Set master mode and sw controlled CS */ 161 reg = readl(®s->command); 162 reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT; 163 writel(reg, ®s->command); 164 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command)); 165 166 return 0; 167 } 168 169 static void spi_cs_activate(struct udevice *dev) 170 { 171 struct udevice *bus = dev->parent; 172 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 173 struct tegra30_spi_priv *priv = dev_get_priv(bus); 174 175 /* If it's too soon to do another transaction, wait */ 176 if (pdata->deactivate_delay_us && 177 priv->last_transaction_us) { 178 ulong delay_us; /* The delay completed so far */ 179 delay_us = timer_get_us() - priv->last_transaction_us; 180 if (delay_us < pdata->deactivate_delay_us) 181 udelay(pdata->deactivate_delay_us - delay_us); 182 } 183 184 /* CS is negated on Tegra, so drive a 1 to get a 0 */ 185 setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL); 186 } 187 188 static void spi_cs_deactivate(struct udevice *dev) 189 { 190 struct udevice *bus = dev->parent; 191 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 192 struct tegra30_spi_priv *priv = dev_get_priv(bus); 193 194 /* CS is negated on Tegra, so drive a 0 to get a 1 */ 195 clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL); 196 197 /* Remember time of this transaction so we can honour the bus delay */ 198 if (pdata->deactivate_delay_us) 199 priv->last_transaction_us = timer_get_us(); 200 } 201 202 static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen, 203 const void *data_out, void *data_in, 204 unsigned long flags) 205 { 206 struct udevice *bus = dev->parent; 207 struct tegra30_spi_priv *priv = dev_get_priv(bus); 208 struct spi_regs *regs = priv->regs; 209 u32 reg, tmpdout, tmpdin = 0; 210 const u8 *dout = data_out; 211 u8 *din = data_in; 212 int num_bytes; 213 int ret; 214 215 debug("%s: slave %u:%u dout %p din %p bitlen %u\n", 216 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); 217 if (bitlen % 8) 218 return -1; 219 num_bytes = bitlen / 8; 220 221 ret = 0; 222 223 reg = readl(®s->status); 224 writel(reg, ®s->status); /* Clear all SPI events via R/W */ 225 debug("%s entry: STATUS = %08x\n", __func__, reg); 226 227 reg = readl(®s->status2); 228 writel(reg, ®s->status2); /* Clear all STATUS2 events via R/W */ 229 debug("%s entry: STATUS2 = %08x\n", __func__, reg); 230 231 debug("%s entry: COMMAND = %08x\n", __func__, readl(®s->command)); 232 233 clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK, 234 SLINK_CMD2_TXEN | SLINK_CMD2_RXEN | 235 (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT)); 236 debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2)); 237 238 if (flags & SPI_XFER_BEGIN) 239 spi_cs_activate(dev); 240 241 /* handle data in 32-bit chunks */ 242 while (num_bytes > 0) { 243 int bytes; 244 int is_read = 0; 245 int tm, i; 246 247 tmpdout = 0; 248 bytes = (num_bytes > 4) ? 4 : num_bytes; 249 250 if (dout != NULL) { 251 for (i = 0; i < bytes; ++i) 252 tmpdout = (tmpdout << 8) | dout[i]; 253 dout += bytes; 254 } 255 256 num_bytes -= bytes; 257 258 clrsetbits_le32(®s->command, SLINK_CMD_BIT_LENGTH_MASK, 259 bytes * 8 - 1); 260 writel(tmpdout, ®s->tx_fifo); 261 setbits_le32(®s->command, SLINK_CMD_GO); 262 263 /* 264 * Wait for SPI transmit FIFO to empty, or to time out. 265 * The RX FIFO status will be read and cleared last 266 */ 267 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { 268 u32 status; 269 270 status = readl(®s->status); 271 272 /* We can exit when we've had both RX and TX activity */ 273 if (is_read && (status & SLINK_STAT_TXF_EMPTY)) 274 break; 275 276 if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) != 277 SLINK_STAT_RDY) 278 tm++; 279 280 else if (!(status & SLINK_STAT_RXF_EMPTY)) { 281 tmpdin = readl(®s->rx_fifo); 282 is_read = 1; 283 284 /* swap bytes read in */ 285 if (din != NULL) { 286 for (i = bytes - 1; i >= 0; --i) { 287 din[i] = tmpdin & 0xff; 288 tmpdin >>= 8; 289 } 290 din += bytes; 291 } 292 } 293 } 294 295 if (tm >= SPI_TIMEOUT) 296 ret = tm; 297 298 /* clear ACK RDY, etc. bits */ 299 writel(readl(®s->status), ®s->status); 300 } 301 302 if (flags & SPI_XFER_END) 303 spi_cs_deactivate(dev); 304 305 debug("%s: transfer ended. Value=%08x, status = %08x\n", 306 __func__, tmpdin, readl(®s->status)); 307 308 if (ret) { 309 printf("%s: timeout during SPI transfer, tm %d\n", 310 __func__, ret); 311 return -1; 312 } 313 314 return 0; 315 } 316 317 static int tegra30_spi_set_speed(struct udevice *bus, uint speed) 318 { 319 struct tegra_spi_platdata *plat = bus->platdata; 320 struct tegra30_spi_priv *priv = dev_get_priv(bus); 321 322 if (speed > plat->frequency) 323 speed = plat->frequency; 324 priv->freq = speed; 325 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); 326 327 return 0; 328 } 329 330 static int tegra30_spi_set_mode(struct udevice *bus, uint mode) 331 { 332 struct tegra30_spi_priv *priv = dev_get_priv(bus); 333 334 priv->mode = mode; 335 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); 336 337 return 0; 338 } 339 340 static const struct dm_spi_ops tegra30_spi_ops = { 341 .claim_bus = tegra30_spi_claim_bus, 342 .xfer = tegra30_spi_xfer, 343 .set_speed = tegra30_spi_set_speed, 344 .set_mode = tegra30_spi_set_mode, 345 /* 346 * cs_info is not needed, since we require all chip selects to be 347 * in the device tree explicitly 348 */ 349 }; 350 351 static const struct udevice_id tegra30_spi_ids[] = { 352 { .compatible = "nvidia,tegra20-slink" }, 353 { } 354 }; 355 356 U_BOOT_DRIVER(tegra30_spi) = { 357 .name = "tegra20_slink", 358 .id = UCLASS_SPI, 359 .of_match = tegra30_spi_ids, 360 .ops = &tegra30_spi_ops, 361 .ofdata_to_platdata = tegra30_spi_ofdata_to_platdata, 362 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), 363 .priv_auto_alloc_size = sizeof(struct tegra30_spi_priv), 364 .per_child_auto_alloc_size = sizeof(struct spi_slave), 365 .probe = tegra30_spi_probe, 366 }; 367