1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVIDIA Tegra SPI-SLINK controller 4 * 5 * Copyright (c) 2010-2013 NVIDIA Corporation 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch-tegra/clk_rst.h> 13 #include <spi.h> 14 #include <fdtdec.h> 15 #include "tegra_spi.h" 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 /* COMMAND */ 20 #define SLINK_CMD_ENB BIT(31) 21 #define SLINK_CMD_GO BIT(30) 22 #define SLINK_CMD_M_S BIT(28) 23 #define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24) 24 #define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH BIT(24) 25 #define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24) 26 #define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24) 27 #define SLINK_CMD_IDLE_SCLK_MASK (3 << 24) 28 #define SLINK_CMD_CK_SDA BIT(21) 29 #define SLINK_CMD_CS_POL BIT(13) 30 #define SLINK_CMD_CS_VAL BIT(12) 31 #define SLINK_CMD_CS_SOFT BIT(11) 32 #define SLINK_CMD_BIT_LENGTH BIT(4) 33 #define SLINK_CMD_BIT_LENGTH_MASK GENMASK(4, 0) 34 /* COMMAND2 */ 35 #define SLINK_CMD2_TXEN BIT(30) 36 #define SLINK_CMD2_RXEN BIT(31) 37 #define SLINK_CMD2_SS_EN BIT(18) 38 #define SLINK_CMD2_SS_EN_SHIFT 18 39 #define SLINK_CMD2_SS_EN_MASK GENMASK(19, 18) 40 #define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17) 41 /* STATUS */ 42 #define SLINK_STAT_BSY BIT(31) 43 #define SLINK_STAT_RDY BIT(30) 44 #define SLINK_STAT_ERR BIT(29) 45 #define SLINK_STAT_RXF_FLUSH BIT(27) 46 #define SLINK_STAT_TXF_FLUSH BIT(26) 47 #define SLINK_STAT_RXF_OVF BIT(25) 48 #define SLINK_STAT_TXF_UNR BIT(24) 49 #define SLINK_STAT_RXF_EMPTY BIT(23) 50 #define SLINK_STAT_RXF_FULL BIT(22) 51 #define SLINK_STAT_TXF_EMPTY BIT(21) 52 #define SLINK_STAT_TXF_FULL BIT(20) 53 #define SLINK_STAT_TXF_OVF BIT(19) 54 #define SLINK_STAT_RXF_UNR BIT(18) 55 #define SLINK_STAT_CUR_BLKCNT BIT(15) 56 /* STATUS2 */ 57 #define SLINK_STAT2_RXF_FULL_CNT BIT(16) 58 #define SLINK_STAT2_TXF_FULL_CNT BIT(0) 59 60 #define SPI_TIMEOUT 1000 61 #define TEGRA_SPI_MAX_FREQ 52000000 62 63 struct spi_regs { 64 u32 command; /* SLINK_COMMAND_0 register */ 65 u32 command2; /* SLINK_COMMAND2_0 reg */ 66 u32 status; /* SLINK_STATUS_0 register */ 67 u32 reserved; /* Reserved offset 0C */ 68 u32 mas_data; /* SLINK_MAS_DATA_0 reg */ 69 u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */ 70 u32 dma_ctl; /* SLINK_DMA_CTL_0 register */ 71 u32 status2; /* SLINK_STATUS2_0 reg */ 72 u32 rsvd[56]; /* 0x20 to 0xFF reserved */ 73 u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */ 74 u32 rsvd2[31]; /* 0x104 to 0x17F reserved */ 75 u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */ 76 }; 77 78 struct tegra30_spi_priv { 79 struct spi_regs *regs; 80 unsigned int freq; 81 unsigned int mode; 82 int periph_id; 83 int valid; 84 int last_transaction_us; 85 }; 86 87 struct tegra_spi_slave { 88 struct spi_slave slave; 89 struct tegra30_spi_priv *ctrl; 90 }; 91 92 static int tegra30_spi_ofdata_to_platdata(struct udevice *bus) 93 { 94 struct tegra_spi_platdata *plat = bus->platdata; 95 const void *blob = gd->fdt_blob; 96 int node = dev_of_offset(bus); 97 98 plat->base = devfdt_get_addr(bus); 99 plat->periph_id = clock_decode_periph_id(bus); 100 101 if (plat->periph_id == PERIPH_ID_NONE) { 102 debug("%s: could not decode periph id %d\n", __func__, 103 plat->periph_id); 104 return -FDT_ERR_NOTFOUND; 105 } 106 107 /* Use 500KHz as a suitable default */ 108 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 109 500000); 110 plat->deactivate_delay_us = fdtdec_get_int(blob, node, 111 "spi-deactivate-delay", 0); 112 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", 113 __func__, plat->base, plat->periph_id, plat->frequency, 114 plat->deactivate_delay_us); 115 116 return 0; 117 } 118 119 static int tegra30_spi_probe(struct udevice *bus) 120 { 121 struct tegra_spi_platdata *plat = dev_get_platdata(bus); 122 struct tegra30_spi_priv *priv = dev_get_priv(bus); 123 124 priv->regs = (struct spi_regs *)plat->base; 125 126 priv->last_transaction_us = timer_get_us(); 127 priv->freq = plat->frequency; 128 priv->periph_id = plat->periph_id; 129 130 /* Change SPI clock to correct frequency, PLLP_OUT0 source */ 131 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, 132 priv->freq); 133 134 return 0; 135 } 136 137 static int tegra30_spi_claim_bus(struct udevice *dev) 138 { 139 struct udevice *bus = dev->parent; 140 struct tegra30_spi_priv *priv = dev_get_priv(bus); 141 struct spi_regs *regs = priv->regs; 142 u32 reg; 143 144 /* Change SPI clock to correct frequency, PLLP_OUT0 source */ 145 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, 146 priv->freq); 147 148 /* Clear stale status here */ 149 reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \ 150 SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF; 151 writel(reg, ®s->status); 152 debug("%s: STATUS = %08x\n", __func__, readl(®s->status)); 153 154 /* Set master mode and sw controlled CS */ 155 reg = readl(®s->command); 156 reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT; 157 writel(reg, ®s->command); 158 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command)); 159 160 return 0; 161 } 162 163 static void spi_cs_activate(struct udevice *dev) 164 { 165 struct udevice *bus = dev->parent; 166 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 167 struct tegra30_spi_priv *priv = dev_get_priv(bus); 168 169 /* If it's too soon to do another transaction, wait */ 170 if (pdata->deactivate_delay_us && 171 priv->last_transaction_us) { 172 ulong delay_us; /* The delay completed so far */ 173 delay_us = timer_get_us() - priv->last_transaction_us; 174 if (delay_us < pdata->deactivate_delay_us) 175 udelay(pdata->deactivate_delay_us - delay_us); 176 } 177 178 /* CS is negated on Tegra, so drive a 1 to get a 0 */ 179 setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL); 180 } 181 182 static void spi_cs_deactivate(struct udevice *dev) 183 { 184 struct udevice *bus = dev->parent; 185 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 186 struct tegra30_spi_priv *priv = dev_get_priv(bus); 187 188 /* CS is negated on Tegra, so drive a 0 to get a 1 */ 189 clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL); 190 191 /* Remember time of this transaction so we can honour the bus delay */ 192 if (pdata->deactivate_delay_us) 193 priv->last_transaction_us = timer_get_us(); 194 } 195 196 static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen, 197 const void *data_out, void *data_in, 198 unsigned long flags) 199 { 200 struct udevice *bus = dev->parent; 201 struct tegra30_spi_priv *priv = dev_get_priv(bus); 202 struct spi_regs *regs = priv->regs; 203 u32 reg, tmpdout, tmpdin = 0; 204 const u8 *dout = data_out; 205 u8 *din = data_in; 206 int num_bytes; 207 int ret; 208 209 debug("%s: slave %u:%u dout %p din %p bitlen %u\n", 210 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); 211 if (bitlen % 8) 212 return -1; 213 num_bytes = bitlen / 8; 214 215 ret = 0; 216 217 reg = readl(®s->status); 218 writel(reg, ®s->status); /* Clear all SPI events via R/W */ 219 debug("%s entry: STATUS = %08x\n", __func__, reg); 220 221 reg = readl(®s->status2); 222 writel(reg, ®s->status2); /* Clear all STATUS2 events via R/W */ 223 debug("%s entry: STATUS2 = %08x\n", __func__, reg); 224 225 debug("%s entry: COMMAND = %08x\n", __func__, readl(®s->command)); 226 227 clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK, 228 SLINK_CMD2_TXEN | SLINK_CMD2_RXEN | 229 (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT)); 230 debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2)); 231 232 if (flags & SPI_XFER_BEGIN) 233 spi_cs_activate(dev); 234 235 /* handle data in 32-bit chunks */ 236 while (num_bytes > 0) { 237 int bytes; 238 int is_read = 0; 239 int tm, i; 240 241 tmpdout = 0; 242 bytes = (num_bytes > 4) ? 4 : num_bytes; 243 244 if (dout != NULL) { 245 for (i = 0; i < bytes; ++i) 246 tmpdout = (tmpdout << 8) | dout[i]; 247 dout += bytes; 248 } 249 250 num_bytes -= bytes; 251 252 clrsetbits_le32(®s->command, SLINK_CMD_BIT_LENGTH_MASK, 253 bytes * 8 - 1); 254 writel(tmpdout, ®s->tx_fifo); 255 setbits_le32(®s->command, SLINK_CMD_GO); 256 257 /* 258 * Wait for SPI transmit FIFO to empty, or to time out. 259 * The RX FIFO status will be read and cleared last 260 */ 261 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { 262 u32 status; 263 264 status = readl(®s->status); 265 266 /* We can exit when we've had both RX and TX activity */ 267 if (is_read && (status & SLINK_STAT_TXF_EMPTY)) 268 break; 269 270 if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) != 271 SLINK_STAT_RDY) 272 tm++; 273 274 else if (!(status & SLINK_STAT_RXF_EMPTY)) { 275 tmpdin = readl(®s->rx_fifo); 276 is_read = 1; 277 278 /* swap bytes read in */ 279 if (din != NULL) { 280 for (i = bytes - 1; i >= 0; --i) { 281 din[i] = tmpdin & 0xff; 282 tmpdin >>= 8; 283 } 284 din += bytes; 285 } 286 } 287 } 288 289 if (tm >= SPI_TIMEOUT) 290 ret = tm; 291 292 /* clear ACK RDY, etc. bits */ 293 writel(readl(®s->status), ®s->status); 294 } 295 296 if (flags & SPI_XFER_END) 297 spi_cs_deactivate(dev); 298 299 debug("%s: transfer ended. Value=%08x, status = %08x\n", 300 __func__, tmpdin, readl(®s->status)); 301 302 if (ret) { 303 printf("%s: timeout during SPI transfer, tm %d\n", 304 __func__, ret); 305 return -1; 306 } 307 308 return 0; 309 } 310 311 static int tegra30_spi_set_speed(struct udevice *bus, uint speed) 312 { 313 struct tegra_spi_platdata *plat = bus->platdata; 314 struct tegra30_spi_priv *priv = dev_get_priv(bus); 315 316 if (speed > plat->frequency) 317 speed = plat->frequency; 318 priv->freq = speed; 319 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); 320 321 return 0; 322 } 323 324 static int tegra30_spi_set_mode(struct udevice *bus, uint mode) 325 { 326 struct tegra30_spi_priv *priv = dev_get_priv(bus); 327 struct spi_regs *regs = priv->regs; 328 u32 reg; 329 330 reg = readl(®s->command); 331 332 /* Set CPOL and CPHA */ 333 reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA); 334 if (mode & SPI_CPHA) 335 reg |= SLINK_CMD_CK_SDA; 336 337 if (mode & SPI_CPOL) 338 reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH; 339 else 340 reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW; 341 342 writel(reg, ®s->command); 343 344 priv->mode = mode; 345 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); 346 347 return 0; 348 } 349 350 static const struct dm_spi_ops tegra30_spi_ops = { 351 .claim_bus = tegra30_spi_claim_bus, 352 .xfer = tegra30_spi_xfer, 353 .set_speed = tegra30_spi_set_speed, 354 .set_mode = tegra30_spi_set_mode, 355 /* 356 * cs_info is not needed, since we require all chip selects to be 357 * in the device tree explicitly 358 */ 359 }; 360 361 static const struct udevice_id tegra30_spi_ids[] = { 362 { .compatible = "nvidia,tegra20-slink" }, 363 { } 364 }; 365 366 U_BOOT_DRIVER(tegra30_spi) = { 367 .name = "tegra20_slink", 368 .id = UCLASS_SPI, 369 .of_match = tegra30_spi_ids, 370 .ops = &tegra30_spi_ops, 371 .ofdata_to_platdata = tegra30_spi_ofdata_to_platdata, 372 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), 373 .priv_auto_alloc_size = sizeof(struct tegra30_spi_priv), 374 .probe = tegra30_spi_probe, 375 }; 376