1 /* 2 * Copyright (c) 2010-2013 NVIDIA Corporation 3 * With help from the mpc8xxx SPI driver 4 * With more help from omap3_spi SPI driver 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <asm/io.h> 13 #include <asm/gpio.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/arch-tegra/clk_rst.h> 17 #include <spi.h> 18 #include <fdtdec.h> 19 #include "tegra_spi.h" 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 #define SPI_CMD_GO BIT(30) 24 #define SPI_CMD_ACTIVE_SCLK_SHIFT 26 25 #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT) 26 #define SPI_CMD_CK_SDA BIT(21) 27 #define SPI_CMD_ACTIVE_SDA_SHIFT 18 28 #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT) 29 #define SPI_CMD_CS_POL BIT(16) 30 #define SPI_CMD_TXEN BIT(15) 31 #define SPI_CMD_RXEN BIT(14) 32 #define SPI_CMD_CS_VAL BIT(13) 33 #define SPI_CMD_CS_SOFT BIT(12) 34 #define SPI_CMD_CS_DELAY BIT(9) 35 #define SPI_CMD_CS3_EN BIT(8) 36 #define SPI_CMD_CS2_EN BIT(7) 37 #define SPI_CMD_CS1_EN BIT(6) 38 #define SPI_CMD_CS0_EN BIT(5) 39 #define SPI_CMD_BIT_LENGTH BIT(4) 40 #define SPI_CMD_BIT_LENGTH_MASK GENMASK(4, 0) 41 42 #define SPI_STAT_BSY BIT(31) 43 #define SPI_STAT_RDY BIT(30) 44 #define SPI_STAT_RXF_FLUSH BIT(29) 45 #define SPI_STAT_TXF_FLUSH BIT(28) 46 #define SPI_STAT_RXF_UNR BIT(27) 47 #define SPI_STAT_TXF_OVF BIT(26) 48 #define SPI_STAT_RXF_EMPTY BIT(25) 49 #define SPI_STAT_RXF_FULL BIT(24) 50 #define SPI_STAT_TXF_EMPTY BIT(23) 51 #define SPI_STAT_TXF_FULL BIT(22) 52 #define SPI_STAT_SEL_TXRX_N BIT(16) 53 #define SPI_STAT_CUR_BLKCNT BIT(15) 54 55 #define SPI_TIMEOUT 1000 56 #define TEGRA_SPI_MAX_FREQ 52000000 57 58 struct spi_regs { 59 u32 command; /* SPI_COMMAND_0 register */ 60 u32 status; /* SPI_STATUS_0 register */ 61 u32 rx_cmp; /* SPI_RX_CMP_0 register */ 62 u32 dma_ctl; /* SPI_DMA_CTL_0 register */ 63 u32 tx_fifo; /* SPI_TX_FIFO_0 register */ 64 u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */ 65 u32 rx_fifo; /* SPI_RX_FIFO_0 register */ 66 }; 67 68 struct tegra20_sflash_priv { 69 struct spi_regs *regs; 70 unsigned int freq; 71 unsigned int mode; 72 int periph_id; 73 int valid; 74 int last_transaction_us; 75 }; 76 77 int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs, 78 struct spi_cs_info *info) 79 { 80 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */ 81 if (cs != 0) 82 return -ENODEV; 83 else 84 return 0; 85 } 86 87 static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus) 88 { 89 struct tegra_spi_platdata *plat = bus->platdata; 90 const void *blob = gd->fdt_blob; 91 int node = bus->of_offset; 92 93 plat->base = dev_get_addr(bus); 94 plat->periph_id = clock_decode_periph_id(blob, node); 95 96 if (plat->periph_id == PERIPH_ID_NONE) { 97 debug("%s: could not decode periph id %d\n", __func__, 98 plat->periph_id); 99 return -FDT_ERR_NOTFOUND; 100 } 101 102 /* Use 500KHz as a suitable default */ 103 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 104 500000); 105 plat->deactivate_delay_us = fdtdec_get_int(blob, node, 106 "spi-deactivate-delay", 0); 107 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", 108 __func__, plat->base, plat->periph_id, plat->frequency, 109 plat->deactivate_delay_us); 110 111 return 0; 112 } 113 114 static int tegra20_sflash_probe(struct udevice *bus) 115 { 116 struct tegra_spi_platdata *plat = dev_get_platdata(bus); 117 struct tegra20_sflash_priv *priv = dev_get_priv(bus); 118 119 priv->regs = (struct spi_regs *)plat->base; 120 121 priv->last_transaction_us = timer_get_us(); 122 priv->freq = plat->frequency; 123 priv->periph_id = plat->periph_id; 124 125 return 0; 126 } 127 128 static int tegra20_sflash_claim_bus(struct udevice *dev) 129 { 130 struct udevice *bus = dev->parent; 131 struct tegra20_sflash_priv *priv = dev_get_priv(bus); 132 struct spi_regs *regs = priv->regs; 133 u32 reg; 134 135 /* Change SPI clock to correct frequency, PLLP_OUT0 source */ 136 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, 137 priv->freq); 138 139 /* Clear stale status here */ 140 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \ 141 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF; 142 writel(reg, ®s->status); 143 debug("%s: STATUS = %08x\n", __func__, readl(®s->status)); 144 145 /* 146 * Use sw-controlled CS, so we can clock in data after ReadID, etc. 147 */ 148 reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT; 149 if (priv->mode & 2) 150 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT; 151 clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK | 152 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg); 153 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command)); 154 155 /* 156 * SPI pins on Tegra20 are muxed - change pinmux later due to UART 157 * issue. 158 */ 159 pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH); 160 pinmux_tristate_disable(PMUX_PINGRP_LSPI); 161 pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH); 162 163 return 0; 164 } 165 166 static void spi_cs_activate(struct udevice *dev) 167 { 168 struct udevice *bus = dev->parent; 169 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 170 struct tegra20_sflash_priv *priv = dev_get_priv(bus); 171 172 /* If it's too soon to do another transaction, wait */ 173 if (pdata->deactivate_delay_us && 174 priv->last_transaction_us) { 175 ulong delay_us; /* The delay completed so far */ 176 delay_us = timer_get_us() - priv->last_transaction_us; 177 if (delay_us < pdata->deactivate_delay_us) 178 udelay(pdata->deactivate_delay_us - delay_us); 179 } 180 181 /* CS is negated on Tegra, so drive a 1 to get a 0 */ 182 setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL); 183 } 184 185 static void spi_cs_deactivate(struct udevice *dev) 186 { 187 struct udevice *bus = dev->parent; 188 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 189 struct tegra20_sflash_priv *priv = dev_get_priv(bus); 190 191 /* CS is negated on Tegra, so drive a 0 to get a 1 */ 192 clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL); 193 194 /* Remember time of this transaction so we can honour the bus delay */ 195 if (pdata->deactivate_delay_us) 196 priv->last_transaction_us = timer_get_us(); 197 } 198 199 static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen, 200 const void *data_out, void *data_in, 201 unsigned long flags) 202 { 203 struct udevice *bus = dev->parent; 204 struct tegra20_sflash_priv *priv = dev_get_priv(bus); 205 struct spi_regs *regs = priv->regs; 206 u32 reg, tmpdout, tmpdin = 0; 207 const u8 *dout = data_out; 208 u8 *din = data_in; 209 int num_bytes; 210 int ret; 211 212 debug("%s: slave %u:%u dout %p din %p bitlen %u\n", 213 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); 214 if (bitlen % 8) 215 return -1; 216 num_bytes = bitlen / 8; 217 218 ret = 0; 219 220 reg = readl(®s->status); 221 writel(reg, ®s->status); /* Clear all SPI events via R/W */ 222 debug("spi_xfer entry: STATUS = %08x\n", reg); 223 224 reg = readl(®s->command); 225 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN; 226 writel(reg, ®s->command); 227 debug("spi_xfer: COMMAND = %08x\n", readl(®s->command)); 228 229 if (flags & SPI_XFER_BEGIN) 230 spi_cs_activate(dev); 231 232 /* handle data in 32-bit chunks */ 233 while (num_bytes > 0) { 234 int bytes; 235 int is_read = 0; 236 int tm, i; 237 238 tmpdout = 0; 239 bytes = (num_bytes > 4) ? 4 : num_bytes; 240 241 if (dout != NULL) { 242 for (i = 0; i < bytes; ++i) 243 tmpdout = (tmpdout << 8) | dout[i]; 244 } 245 246 num_bytes -= bytes; 247 if (dout) 248 dout += bytes; 249 250 clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK, 251 bytes * 8 - 1); 252 writel(tmpdout, ®s->tx_fifo); 253 setbits_le32(®s->command, SPI_CMD_GO); 254 255 /* 256 * Wait for SPI transmit FIFO to empty, or to time out. 257 * The RX FIFO status will be read and cleared last 258 */ 259 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { 260 u32 status; 261 262 status = readl(®s->status); 263 264 /* We can exit when we've had both RX and TX activity */ 265 if (is_read && (status & SPI_STAT_TXF_EMPTY)) 266 break; 267 268 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) != 269 SPI_STAT_RDY) 270 tm++; 271 272 else if (!(status & SPI_STAT_RXF_EMPTY)) { 273 tmpdin = readl(®s->rx_fifo); 274 is_read = 1; 275 276 /* swap bytes read in */ 277 if (din != NULL) { 278 for (i = bytes - 1; i >= 0; --i) { 279 din[i] = tmpdin & 0xff; 280 tmpdin >>= 8; 281 } 282 din += bytes; 283 } 284 } 285 } 286 287 if (tm >= SPI_TIMEOUT) 288 ret = tm; 289 290 /* clear ACK RDY, etc. bits */ 291 writel(readl(®s->status), ®s->status); 292 } 293 294 if (flags & SPI_XFER_END) 295 spi_cs_deactivate(dev); 296 297 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n", 298 tmpdin, readl(®s->status)); 299 300 if (ret) { 301 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret); 302 return -1; 303 } 304 305 return 0; 306 } 307 308 static int tegra20_sflash_set_speed(struct udevice *bus, uint speed) 309 { 310 struct tegra_spi_platdata *plat = bus->platdata; 311 struct tegra20_sflash_priv *priv = dev_get_priv(bus); 312 313 if (speed > plat->frequency) 314 speed = plat->frequency; 315 priv->freq = speed; 316 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); 317 318 return 0; 319 } 320 321 static int tegra20_sflash_set_mode(struct udevice *bus, uint mode) 322 { 323 struct tegra20_sflash_priv *priv = dev_get_priv(bus); 324 325 priv->mode = mode; 326 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); 327 328 return 0; 329 } 330 331 static const struct dm_spi_ops tegra20_sflash_ops = { 332 .claim_bus = tegra20_sflash_claim_bus, 333 .xfer = tegra20_sflash_xfer, 334 .set_speed = tegra20_sflash_set_speed, 335 .set_mode = tegra20_sflash_set_mode, 336 .cs_info = tegra20_sflash_cs_info, 337 }; 338 339 static const struct udevice_id tegra20_sflash_ids[] = { 340 { .compatible = "nvidia,tegra20-sflash" }, 341 { } 342 }; 343 344 U_BOOT_DRIVER(tegra20_sflash) = { 345 .name = "tegra20_sflash", 346 .id = UCLASS_SPI, 347 .of_match = tegra20_sflash_ids, 348 .ops = &tegra20_sflash_ops, 349 .ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata, 350 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), 351 .priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv), 352 .probe = tegra20_sflash_probe, 353 }; 354