1 /* 2 * Copyright (c) 2010-2013 NVIDIA Corporation 3 * With help from the mpc8xxx SPI driver 4 * With more help from omap3_spi SPI driver 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <malloc.h> 27 #include <asm/io.h> 28 #include <asm/gpio.h> 29 #include <asm/arch/clock.h> 30 #include <asm/arch/pinmux.h> 31 #include <asm/arch-tegra/clk_rst.h> 32 #include <asm/arch-tegra20/tegra20_sflash.h> 33 #include <spi.h> 34 #include <fdtdec.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 #define SPI_CMD_GO (1 << 30) 39 #define SPI_CMD_ACTIVE_SCLK_SHIFT 26 40 #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT) 41 #define SPI_CMD_CK_SDA (1 << 21) 42 #define SPI_CMD_ACTIVE_SDA_SHIFT 18 43 #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT) 44 #define SPI_CMD_CS_POL (1 << 16) 45 #define SPI_CMD_TXEN (1 << 15) 46 #define SPI_CMD_RXEN (1 << 14) 47 #define SPI_CMD_CS_VAL (1 << 13) 48 #define SPI_CMD_CS_SOFT (1 << 12) 49 #define SPI_CMD_CS_DELAY (1 << 9) 50 #define SPI_CMD_CS3_EN (1 << 8) 51 #define SPI_CMD_CS2_EN (1 << 7) 52 #define SPI_CMD_CS1_EN (1 << 6) 53 #define SPI_CMD_CS0_EN (1 << 5) 54 #define SPI_CMD_BIT_LENGTH (1 << 4) 55 #define SPI_CMD_BIT_LENGTH_MASK 0x0000001F 56 57 #define SPI_STAT_BSY (1 << 31) 58 #define SPI_STAT_RDY (1 << 30) 59 #define SPI_STAT_RXF_FLUSH (1 << 29) 60 #define SPI_STAT_TXF_FLUSH (1 << 28) 61 #define SPI_STAT_RXF_UNR (1 << 27) 62 #define SPI_STAT_TXF_OVF (1 << 26) 63 #define SPI_STAT_RXF_EMPTY (1 << 25) 64 #define SPI_STAT_RXF_FULL (1 << 24) 65 #define SPI_STAT_TXF_EMPTY (1 << 23) 66 #define SPI_STAT_TXF_FULL (1 << 22) 67 #define SPI_STAT_SEL_TXRX_N (1 << 16) 68 #define SPI_STAT_CUR_BLKCNT (1 << 15) 69 70 #define SPI_TIMEOUT 1000 71 #define TEGRA_SPI_MAX_FREQ 52000000 72 73 struct spi_regs { 74 u32 command; /* SPI_COMMAND_0 register */ 75 u32 status; /* SPI_STATUS_0 register */ 76 u32 rx_cmp; /* SPI_RX_CMP_0 register */ 77 u32 dma_ctl; /* SPI_DMA_CTL_0 register */ 78 u32 tx_fifo; /* SPI_TX_FIFO_0 register */ 79 u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */ 80 u32 rx_fifo; /* SPI_RX_FIFO_0 register */ 81 }; 82 83 struct tegra_spi_ctrl { 84 struct spi_regs *regs; 85 unsigned int freq; 86 unsigned int mode; 87 int periph_id; 88 int valid; 89 }; 90 91 struct tegra_spi_slave { 92 struct spi_slave slave; 93 struct tegra_spi_ctrl *ctrl; 94 }; 95 96 /* tegra20 only supports one SFLASH controller */ 97 static struct tegra_spi_ctrl spi_ctrls[1]; 98 99 static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) 100 { 101 return container_of(slave, struct tegra_spi_slave, slave); 102 } 103 104 int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs) 105 { 106 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */ 107 if (bus != 0 || cs != 0) 108 return 0; 109 else 110 return 1; 111 } 112 113 struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs, 114 unsigned int max_hz, unsigned int mode) 115 { 116 struct tegra_spi_slave *spi; 117 118 if (!spi_cs_is_valid(bus, cs)) { 119 printf("SPI error: unsupported bus %d / chip select %d\n", 120 bus, cs); 121 return NULL; 122 } 123 124 if (max_hz > TEGRA_SPI_MAX_FREQ) { 125 printf("SPI error: unsupported frequency %d Hz. Max frequency" 126 " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ); 127 return NULL; 128 } 129 130 spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs); 131 if (!spi) { 132 printf("SPI error: malloc of SPI structure failed\n"); 133 return NULL; 134 } 135 spi->slave.bus = bus; 136 spi->slave.cs = cs; 137 spi->ctrl = &spi_ctrls[bus]; 138 if (!spi->ctrl) { 139 printf("SPI error: could not find controller for bus %d\n", 140 bus); 141 return NULL; 142 } 143 144 if (max_hz < spi->ctrl->freq) { 145 debug("%s: limiting frequency from %u to %u\n", __func__, 146 spi->ctrl->freq, max_hz); 147 spi->ctrl->freq = max_hz; 148 } 149 spi->ctrl->mode = mode; 150 151 return &spi->slave; 152 } 153 154 void tegra20_spi_free_slave(struct spi_slave *slave) 155 { 156 struct tegra_spi_slave *spi = to_tegra_spi(slave); 157 158 free(spi); 159 } 160 161 int tegra20_spi_init(int *node_list, int count) 162 { 163 struct tegra_spi_ctrl *ctrl; 164 int i; 165 int node = 0; 166 int found = 0; 167 168 for (i = 0; i < count; i++) { 169 ctrl = &spi_ctrls[i]; 170 node = node_list[i]; 171 172 ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob, 173 node, "reg"); 174 if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) { 175 debug("%s: no slink register found\n", __func__); 176 continue; 177 } 178 ctrl->freq = fdtdec_get_int(gd->fdt_blob, node, 179 "spi-max-frequency", 0); 180 if (!ctrl->freq) { 181 debug("%s: no slink max frequency found\n", __func__); 182 continue; 183 } 184 185 ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node); 186 if (ctrl->periph_id == PERIPH_ID_NONE) { 187 debug("%s: could not decode periph id\n", __func__); 188 continue; 189 } 190 ctrl->valid = 1; 191 found = 1; 192 193 debug("%s: found controller at %p, freq = %u, periph_id = %d\n", 194 __func__, ctrl->regs, ctrl->freq, ctrl->periph_id); 195 } 196 return !found; 197 } 198 199 int tegra20_spi_claim_bus(struct spi_slave *slave) 200 { 201 struct tegra_spi_slave *spi = to_tegra_spi(slave); 202 struct spi_regs *regs = spi->ctrl->regs; 203 u32 reg; 204 205 /* Change SPI clock to correct frequency, PLLP_OUT0 source */ 206 clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH, 207 spi->ctrl->freq); 208 209 /* Clear stale status here */ 210 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \ 211 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF; 212 writel(reg, ®s->status); 213 debug("%s: STATUS = %08x\n", __func__, readl(®s->status)); 214 215 /* 216 * Use sw-controlled CS, so we can clock in data after ReadID, etc. 217 */ 218 reg = (spi->ctrl->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT; 219 if (spi->ctrl->mode & 2) 220 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT; 221 clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK | 222 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg); 223 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command)); 224 225 /* 226 * SPI pins on Tegra20 are muxed - change pinmux later due to UART 227 * issue. 228 */ 229 pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH); 230 pinmux_tristate_disable(PINGRP_LSPI); 231 pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); 232 233 return 0; 234 } 235 236 void tegra20_spi_cs_activate(struct spi_slave *slave) 237 { 238 struct tegra_spi_slave *spi = to_tegra_spi(slave); 239 struct spi_regs *regs = spi->ctrl->regs; 240 241 /* CS is negated on Tegra, so drive a 1 to get a 0 */ 242 setbits_le32(®s->command, SPI_CMD_CS_VAL); 243 } 244 245 void tegra20_spi_cs_deactivate(struct spi_slave *slave) 246 { 247 struct tegra_spi_slave *spi = to_tegra_spi(slave); 248 struct spi_regs *regs = spi->ctrl->regs; 249 250 /* CS is negated on Tegra, so drive a 0 to get a 1 */ 251 clrbits_le32(®s->command, SPI_CMD_CS_VAL); 252 } 253 254 int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, 255 const void *data_out, void *data_in, unsigned long flags) 256 { 257 struct tegra_spi_slave *spi = to_tegra_spi(slave); 258 struct spi_regs *regs = spi->ctrl->regs; 259 u32 reg, tmpdout, tmpdin = 0; 260 const u8 *dout = data_out; 261 u8 *din = data_in; 262 int num_bytes; 263 int ret; 264 265 debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", 266 slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen); 267 if (bitlen % 8) 268 return -1; 269 num_bytes = bitlen / 8; 270 271 ret = 0; 272 273 reg = readl(®s->status); 274 writel(reg, ®s->status); /* Clear all SPI events via R/W */ 275 debug("spi_xfer entry: STATUS = %08x\n", reg); 276 277 reg = readl(®s->command); 278 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN; 279 writel(reg, ®s->command); 280 debug("spi_xfer: COMMAND = %08x\n", readl(®s->command)); 281 282 if (flags & SPI_XFER_BEGIN) 283 spi_cs_activate(slave); 284 285 /* handle data in 32-bit chunks */ 286 while (num_bytes > 0) { 287 int bytes; 288 int is_read = 0; 289 int tm, i; 290 291 tmpdout = 0; 292 bytes = (num_bytes > 4) ? 4 : num_bytes; 293 294 if (dout != NULL) { 295 for (i = 0; i < bytes; ++i) 296 tmpdout = (tmpdout << 8) | dout[i]; 297 } 298 299 num_bytes -= bytes; 300 if (dout) 301 dout += bytes; 302 303 clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK, 304 bytes * 8 - 1); 305 writel(tmpdout, ®s->tx_fifo); 306 setbits_le32(®s->command, SPI_CMD_GO); 307 308 /* 309 * Wait for SPI transmit FIFO to empty, or to time out. 310 * The RX FIFO status will be read and cleared last 311 */ 312 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { 313 u32 status; 314 315 status = readl(®s->status); 316 317 /* We can exit when we've had both RX and TX activity */ 318 if (is_read && (status & SPI_STAT_TXF_EMPTY)) 319 break; 320 321 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) != 322 SPI_STAT_RDY) 323 tm++; 324 325 else if (!(status & SPI_STAT_RXF_EMPTY)) { 326 tmpdin = readl(®s->rx_fifo); 327 is_read = 1; 328 329 /* swap bytes read in */ 330 if (din != NULL) { 331 for (i = bytes - 1; i >= 0; --i) { 332 din[i] = tmpdin & 0xff; 333 tmpdin >>= 8; 334 } 335 din += bytes; 336 } 337 } 338 } 339 340 if (tm >= SPI_TIMEOUT) 341 ret = tm; 342 343 /* clear ACK RDY, etc. bits */ 344 writel(readl(®s->status), ®s->status); 345 } 346 347 if (flags & SPI_XFER_END) 348 spi_cs_deactivate(slave); 349 350 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n", 351 tmpdin, readl(®s->status)); 352 353 if (ret) { 354 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret); 355 return -1; 356 } 357 358 return 0; 359 } 360