1 /* 2 * NVIDIA Tegra SPI controller (T114 and later) 3 * 4 * Copyright (c) 2010-2013 NVIDIA Corporation 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <asm/io.h> 27 #include <asm/gpio.h> 28 #include <asm/arch/clock.h> 29 #include <asm/arch-tegra/clk_rst.h> 30 #include <asm/arch-tegra114/tegra114_spi.h> 31 #include <spi.h> 32 #include <fdtdec.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 /* COMMAND1 */ 37 #define SPI_CMD1_GO (1 << 31) 38 #define SPI_CMD1_M_S (1 << 30) 39 #define SPI_CMD1_MODE_MASK 0x3 40 #define SPI_CMD1_MODE_SHIFT 28 41 #define SPI_CMD1_CS_SEL_MASK 0x3 42 #define SPI_CMD1_CS_SEL_SHIFT 26 43 #define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25) 44 #define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24) 45 #define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23) 46 #define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22) 47 #define SPI_CMD1_CS_SW_HW (1 << 21) 48 #define SPI_CMD1_CS_SW_VAL (1 << 20) 49 #define SPI_CMD1_IDLE_SDA_MASK 0x3 50 #define SPI_CMD1_IDLE_SDA_SHIFT 18 51 #define SPI_CMD1_BIDIR (1 << 17) 52 #define SPI_CMD1_LSBI_FE (1 << 16) 53 #define SPI_CMD1_LSBY_FE (1 << 15) 54 #define SPI_CMD1_BOTH_EN_BIT (1 << 14) 55 #define SPI_CMD1_BOTH_EN_BYTE (1 << 13) 56 #define SPI_CMD1_RX_EN (1 << 12) 57 #define SPI_CMD1_TX_EN (1 << 11) 58 #define SPI_CMD1_PACKED (1 << 5) 59 #define SPI_CMD1_BIT_LEN_MASK 0x1F 60 #define SPI_CMD1_BIT_LEN_SHIFT 0 61 62 /* COMMAND2 */ 63 #define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6) 64 #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) 65 #define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0) 66 #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) 67 68 /* TRANSFER STATUS */ 69 #define SPI_XFER_STS_RDY (1 << 30) 70 71 /* FIFO STATUS */ 72 #define SPI_FIFO_STS_CS_INACTIVE (1 << 31) 73 #define SPI_FIFO_STS_FRAME_END (1 << 30) 74 #define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15) 75 #define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14) 76 #define SPI_FIFO_STS_ERR (1 << 8) 77 #define SPI_FIFO_STS_TX_FIFO_OVF (1 << 7) 78 #define SPI_FIFO_STS_TX_FIFO_UNR (1 << 6) 79 #define SPI_FIFO_STS_RX_FIFO_OVF (1 << 5) 80 #define SPI_FIFO_STS_RX_FIFO_UNR (1 << 4) 81 #define SPI_FIFO_STS_TX_FIFO_FULL (1 << 3) 82 #define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2) 83 #define SPI_FIFO_STS_RX_FIFO_FULL (1 << 1) 84 #define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0) 85 86 #define SPI_TIMEOUT 1000 87 #define TEGRA_SPI_MAX_FREQ 52000000 88 89 struct spi_regs { 90 u32 command1; /* 000:SPI_COMMAND1 register */ 91 u32 command2; /* 004:SPI_COMMAND2 register */ 92 u32 timing1; /* 008:SPI_CS_TIM1 register */ 93 u32 timing2; /* 00c:SPI_CS_TIM2 register */ 94 u32 xfer_status;/* 010:SPI_TRANS_STATUS register */ 95 u32 fifo_status;/* 014:SPI_FIFO_STATUS register */ 96 u32 tx_data; /* 018:SPI_TX_DATA register */ 97 u32 rx_data; /* 01c:SPI_RX_DATA register */ 98 u32 dma_ctl; /* 020:SPI_DMA_CTL register */ 99 u32 dma_blk; /* 024:SPI_DMA_BLK register */ 100 u32 rsvd[56]; /* 028-107 reserved */ 101 u32 tx_fifo; /* 108:SPI_FIFO1 register */ 102 u32 rsvd2[31]; /* 10c-187 reserved */ 103 u32 rx_fifo; /* 188:SPI_FIFO2 register */ 104 u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */ 105 }; 106 107 struct tegra_spi_ctrl { 108 struct spi_regs *regs; 109 unsigned int freq; 110 unsigned int mode; 111 int periph_id; 112 int valid; 113 }; 114 115 struct tegra_spi_slave { 116 struct spi_slave slave; 117 struct tegra_spi_ctrl *ctrl; 118 }; 119 120 static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA114_SPI_CTRLS]; 121 122 static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) 123 { 124 return container_of(slave, struct tegra_spi_slave, slave); 125 } 126 127 int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs) 128 { 129 if (bus >= CONFIG_TEGRA114_SPI_CTRLS || cs > 3 || !spi_ctrls[bus].valid) 130 return 0; 131 else 132 return 1; 133 } 134 135 struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs, 136 unsigned int max_hz, unsigned int mode) 137 { 138 struct tegra_spi_slave *spi; 139 140 debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__, 141 bus, cs, max_hz, mode); 142 143 if (!spi_cs_is_valid(bus, cs)) { 144 printf("SPI error: unsupported bus %d / chip select %d\n", 145 bus, cs); 146 return NULL; 147 } 148 149 if (max_hz > TEGRA_SPI_MAX_FREQ) { 150 printf("SPI error: unsupported frequency %d Hz. Max frequency" 151 " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ); 152 return NULL; 153 } 154 155 spi = malloc(sizeof(struct tegra_spi_slave)); 156 if (!spi) { 157 printf("SPI error: malloc of SPI structure failed\n"); 158 return NULL; 159 } 160 spi->slave.bus = bus; 161 spi->slave.cs = cs; 162 spi->ctrl = &spi_ctrls[bus]; 163 if (!spi->ctrl) { 164 printf("SPI error: could not find controller for bus %d\n", 165 bus); 166 return NULL; 167 } 168 169 if (max_hz < spi->ctrl->freq) { 170 debug("%s: limiting frequency from %u to %u\n", __func__, 171 spi->ctrl->freq, max_hz); 172 spi->ctrl->freq = max_hz; 173 } 174 spi->ctrl->mode = mode; 175 176 return &spi->slave; 177 } 178 179 void tegra114_spi_free_slave(struct spi_slave *slave) 180 { 181 struct tegra_spi_slave *spi = to_tegra_spi(slave); 182 183 free(spi); 184 } 185 186 int tegra114_spi_init(int *node_list, int count) 187 { 188 struct tegra_spi_ctrl *ctrl; 189 int i; 190 int node = 0; 191 int found = 0; 192 193 for (i = 0; i < count; i++) { 194 ctrl = &spi_ctrls[i]; 195 node = node_list[i]; 196 197 ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob, 198 node, "reg"); 199 if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) { 200 debug("%s: no spi register found\n", __func__); 201 continue; 202 } 203 ctrl->freq = fdtdec_get_int(gd->fdt_blob, node, 204 "spi-max-frequency", 0); 205 if (!ctrl->freq) { 206 debug("%s: no spi max frequency found\n", __func__); 207 continue; 208 } 209 210 ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node); 211 if (ctrl->periph_id == PERIPH_ID_NONE) { 212 debug("%s: could not decode periph id\n", __func__); 213 continue; 214 } 215 ctrl->valid = 1; 216 found = 1; 217 218 debug("%s: found controller at %p, freq = %u, periph_id = %d\n", 219 __func__, ctrl->regs, ctrl->freq, ctrl->periph_id); 220 } 221 222 return !found; 223 } 224 225 int tegra114_spi_claim_bus(struct spi_slave *slave) 226 { 227 struct tegra_spi_slave *spi = to_tegra_spi(slave); 228 struct spi_regs *regs = spi->ctrl->regs; 229 230 /* Change SPI clock to correct frequency, PLLP_OUT0 source */ 231 clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH, 232 spi->ctrl->freq); 233 234 /* Clear stale status here */ 235 setbits_le32(®s->fifo_status, 236 SPI_FIFO_STS_ERR | 237 SPI_FIFO_STS_TX_FIFO_OVF | 238 SPI_FIFO_STS_TX_FIFO_UNR | 239 SPI_FIFO_STS_RX_FIFO_OVF | 240 SPI_FIFO_STS_RX_FIFO_UNR | 241 SPI_FIFO_STS_TX_FIFO_FULL | 242 SPI_FIFO_STS_TX_FIFO_EMPTY | 243 SPI_FIFO_STS_RX_FIFO_FULL | 244 SPI_FIFO_STS_RX_FIFO_EMPTY); 245 debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); 246 247 /* Set master mode and sw controlled CS */ 248 setbits_le32(®s->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW | 249 (spi->ctrl->mode << SPI_CMD1_MODE_SHIFT)); 250 debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); 251 252 return 0; 253 } 254 255 void tegra114_spi_cs_activate(struct spi_slave *slave) 256 { 257 struct tegra_spi_slave *spi = to_tegra_spi(slave); 258 struct spi_regs *regs = spi->ctrl->regs; 259 260 clrbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL); 261 } 262 263 void tegra114_spi_cs_deactivate(struct spi_slave *slave) 264 { 265 struct tegra_spi_slave *spi = to_tegra_spi(slave); 266 struct spi_regs *regs = spi->ctrl->regs; 267 268 setbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL); 269 } 270 271 int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, 272 const void *data_out, void *data_in, unsigned long flags) 273 { 274 struct tegra_spi_slave *spi = to_tegra_spi(slave); 275 struct spi_regs *regs = spi->ctrl->regs; 276 u32 reg, tmpdout, tmpdin = 0; 277 const u8 *dout = data_out; 278 u8 *din = data_in; 279 int num_bytes; 280 int ret; 281 282 debug("%s: slave %u:%u dout %p din %p bitlen %u\n", 283 __func__, slave->bus, slave->cs, dout, din, bitlen); 284 if (bitlen % 8) 285 return -1; 286 num_bytes = bitlen / 8; 287 288 ret = 0; 289 290 /* clear all error status bits */ 291 reg = readl(®s->fifo_status); 292 writel(reg, ®s->fifo_status); 293 294 /* clear ready bit */ 295 setbits_le32(®s->xfer_status, SPI_XFER_STS_RDY); 296 297 clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL, 298 SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE | 299 (slave->cs << SPI_CMD1_CS_SEL_SHIFT)); 300 301 /* set xfer size to 1 block (32 bits) */ 302 writel(0, ®s->dma_blk); 303 304 if (flags & SPI_XFER_BEGIN) 305 spi_cs_activate(slave); 306 307 /* handle data in 32-bit chunks */ 308 while (num_bytes > 0) { 309 int bytes; 310 int is_read = 0; 311 int tm, i; 312 313 tmpdout = 0; 314 bytes = (num_bytes > 4) ? 4 : num_bytes; 315 316 if (dout != NULL) { 317 for (i = 0; i < bytes; ++i) 318 tmpdout = (tmpdout << 8) | dout[i]; 319 dout += bytes; 320 } 321 322 num_bytes -= bytes; 323 324 clrsetbits_le32(®s->command1, 325 SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT, 326 (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT); 327 writel(tmpdout, ®s->tx_fifo); 328 setbits_le32(®s->command1, SPI_CMD1_GO); 329 330 /* 331 * Wait for SPI transmit FIFO to empty, or to time out. 332 * The RX FIFO status will be read and cleared last 333 */ 334 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { 335 u32 fifo_status, xfer_status; 336 337 fifo_status = readl(®s->fifo_status); 338 339 /* We can exit when we've had both RX and TX activity */ 340 if (is_read && 341 (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)) 342 break; 343 344 xfer_status = readl(®s->xfer_status); 345 if (!(xfer_status & SPI_XFER_STS_RDY)) 346 continue; 347 348 if (fifo_status & SPI_FIFO_STS_ERR) { 349 debug("%s: got a fifo error: ", __func__); 350 if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF) 351 debug("tx FIFO overflow "); 352 if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR) 353 debug("tx FIFO underrun "); 354 if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF) 355 debug("rx FIFO overflow "); 356 if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR) 357 debug("rx FIFO underrun "); 358 if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL) 359 debug("tx FIFO full "); 360 if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY) 361 debug("tx FIFO empty "); 362 if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL) 363 debug("rx FIFO full "); 364 if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY) 365 debug("rx FIFO empty "); 366 debug("\n"); 367 break; 368 } 369 370 if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) { 371 tmpdin = readl(®s->rx_fifo); 372 is_read = 1; 373 374 /* swap bytes read in */ 375 if (din != NULL) { 376 for (i = bytes - 1; i >= 0; --i) { 377 din[i] = tmpdin & 0xff; 378 tmpdin >>= 8; 379 } 380 din += bytes; 381 } 382 } 383 } 384 385 if (tm >= SPI_TIMEOUT) 386 ret = tm; 387 388 /* clear ACK RDY, etc. bits */ 389 writel(readl(®s->fifo_status), ®s->fifo_status); 390 } 391 392 if (flags & SPI_XFER_END) 393 spi_cs_deactivate(slave); 394 395 debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", 396 __func__, tmpdin, readl(®s->fifo_status)); 397 398 if (ret) { 399 printf("%s: timeout during SPI transfer, tm %d\n", 400 __func__, ret); 401 return -1; 402 } 403 404 return 0; 405 } 406