1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVIDIA Tegra SPI controller (T114 and later) 4 * 5 * Copyright (c) 2010-2013 NVIDIA Corporation 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch-tegra/clk_rst.h> 13 #include <spi.h> 14 #include "tegra_spi.h" 15 16 /* COMMAND1 */ 17 #define SPI_CMD1_GO BIT(31) 18 #define SPI_CMD1_M_S BIT(30) 19 #define SPI_CMD1_MODE_MASK GENMASK(1, 0) 20 #define SPI_CMD1_MODE_SHIFT 28 21 #define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0) 22 #define SPI_CMD1_CS_SEL_SHIFT 26 23 #define SPI_CMD1_CS_POL_INACTIVE3 BIT(25) 24 #define SPI_CMD1_CS_POL_INACTIVE2 BIT(24) 25 #define SPI_CMD1_CS_POL_INACTIVE1 BIT(23) 26 #define SPI_CMD1_CS_POL_INACTIVE0 BIT(22) 27 #define SPI_CMD1_CS_SW_HW BIT(21) 28 #define SPI_CMD1_CS_SW_VAL BIT(20) 29 #define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0) 30 #define SPI_CMD1_IDLE_SDA_SHIFT 18 31 #define SPI_CMD1_BIDIR BIT(17) 32 #define SPI_CMD1_LSBI_FE BIT(16) 33 #define SPI_CMD1_LSBY_FE BIT(15) 34 #define SPI_CMD1_BOTH_EN_BIT BIT(14) 35 #define SPI_CMD1_BOTH_EN_BYTE BIT(13) 36 #define SPI_CMD1_RX_EN BIT(12) 37 #define SPI_CMD1_TX_EN BIT(11) 38 #define SPI_CMD1_PACKED BIT(5) 39 #define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0) 40 #define SPI_CMD1_BIT_LEN_SHIFT 0 41 42 /* COMMAND2 */ 43 #define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6) 44 #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6) 45 #define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0) 46 #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0) 47 48 /* TRANSFER STATUS */ 49 #define SPI_XFER_STS_RDY BIT(30) 50 51 /* FIFO STATUS */ 52 #define SPI_FIFO_STS_CS_INACTIVE BIT(31) 53 #define SPI_FIFO_STS_FRAME_END BIT(30) 54 #define SPI_FIFO_STS_RX_FIFO_FLUSH BIT(15) 55 #define SPI_FIFO_STS_TX_FIFO_FLUSH BIT(14) 56 #define SPI_FIFO_STS_ERR BIT(8) 57 #define SPI_FIFO_STS_TX_FIFO_OVF BIT(7) 58 #define SPI_FIFO_STS_TX_FIFO_UNR BIT(6) 59 #define SPI_FIFO_STS_RX_FIFO_OVF BIT(5) 60 #define SPI_FIFO_STS_RX_FIFO_UNR BIT(4) 61 #define SPI_FIFO_STS_TX_FIFO_FULL BIT(3) 62 #define SPI_FIFO_STS_TX_FIFO_EMPTY BIT(2) 63 #define SPI_FIFO_STS_RX_FIFO_FULL BIT(1) 64 #define SPI_FIFO_STS_RX_FIFO_EMPTY BIT(0) 65 66 #define SPI_TIMEOUT 1000 67 #define TEGRA_SPI_MAX_FREQ 52000000 68 69 struct spi_regs { 70 u32 command1; /* 000:SPI_COMMAND1 register */ 71 u32 command2; /* 004:SPI_COMMAND2 register */ 72 u32 timing1; /* 008:SPI_CS_TIM1 register */ 73 u32 timing2; /* 00c:SPI_CS_TIM2 register */ 74 u32 xfer_status;/* 010:SPI_TRANS_STATUS register */ 75 u32 fifo_status;/* 014:SPI_FIFO_STATUS register */ 76 u32 tx_data; /* 018:SPI_TX_DATA register */ 77 u32 rx_data; /* 01c:SPI_RX_DATA register */ 78 u32 dma_ctl; /* 020:SPI_DMA_CTL register */ 79 u32 dma_blk; /* 024:SPI_DMA_BLK register */ 80 u32 rsvd[56]; /* 028-107 reserved */ 81 u32 tx_fifo; /* 108:SPI_FIFO1 register */ 82 u32 rsvd2[31]; /* 10c-187 reserved */ 83 u32 rx_fifo; /* 188:SPI_FIFO2 register */ 84 u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */ 85 }; 86 87 struct tegra114_spi_priv { 88 struct spi_regs *regs; 89 unsigned int freq; 90 unsigned int mode; 91 int periph_id; 92 int valid; 93 int last_transaction_us; 94 }; 95 96 static int tegra114_spi_ofdata_to_platdata(struct udevice *bus) 97 { 98 struct tegra_spi_platdata *plat = bus->platdata; 99 100 plat->base = dev_read_addr(bus); 101 plat->periph_id = clock_decode_periph_id(bus); 102 103 if (plat->periph_id == PERIPH_ID_NONE) { 104 debug("%s: could not decode periph id %d\n", __func__, 105 plat->periph_id); 106 return -FDT_ERR_NOTFOUND; 107 } 108 109 /* Use 500KHz as a suitable default */ 110 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 111 500000); 112 plat->deactivate_delay_us = dev_read_u32_default(bus, 113 "spi-deactivate-delay", 0); 114 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", 115 __func__, plat->base, plat->periph_id, plat->frequency, 116 plat->deactivate_delay_us); 117 118 return 0; 119 } 120 121 static int tegra114_spi_probe(struct udevice *bus) 122 { 123 struct tegra_spi_platdata *plat = dev_get_platdata(bus); 124 struct tegra114_spi_priv *priv = dev_get_priv(bus); 125 struct spi_regs *regs; 126 ulong rate; 127 128 priv->regs = (struct spi_regs *)plat->base; 129 regs = priv->regs; 130 131 priv->last_transaction_us = timer_get_us(); 132 priv->freq = plat->frequency; 133 priv->periph_id = plat->periph_id; 134 135 /* 136 * Change SPI clock to correct frequency, PLLP_OUT0 source, falling 137 * back to the oscillator if that is too fast. 138 */ 139 rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, 140 priv->freq); 141 if (rate > priv->freq + 100000) { 142 rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC, 143 priv->freq); 144 if (rate != priv->freq) { 145 printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n", 146 bus->name, priv->freq, rate); 147 } 148 } 149 udelay(plat->deactivate_delay_us); 150 151 /* Clear stale status here */ 152 setbits_le32(®s->fifo_status, 153 SPI_FIFO_STS_ERR | 154 SPI_FIFO_STS_TX_FIFO_OVF | 155 SPI_FIFO_STS_TX_FIFO_UNR | 156 SPI_FIFO_STS_RX_FIFO_OVF | 157 SPI_FIFO_STS_RX_FIFO_UNR | 158 SPI_FIFO_STS_TX_FIFO_FULL | 159 SPI_FIFO_STS_TX_FIFO_EMPTY | 160 SPI_FIFO_STS_RX_FIFO_FULL | 161 SPI_FIFO_STS_RX_FIFO_EMPTY); 162 debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); 163 164 setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW | 165 (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL); 166 debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); 167 168 return 0; 169 } 170 171 /** 172 * Activate the CS by driving it LOW 173 * 174 * @param slave Pointer to spi_slave to which controller has to 175 * communicate with 176 */ 177 static void spi_cs_activate(struct udevice *dev) 178 { 179 struct udevice *bus = dev->parent; 180 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 181 struct tegra114_spi_priv *priv = dev_get_priv(bus); 182 183 /* If it's too soon to do another transaction, wait */ 184 if (pdata->deactivate_delay_us && 185 priv->last_transaction_us) { 186 ulong delay_us; /* The delay completed so far */ 187 delay_us = timer_get_us() - priv->last_transaction_us; 188 if (delay_us < pdata->deactivate_delay_us) 189 udelay(pdata->deactivate_delay_us - delay_us); 190 } 191 192 clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); 193 } 194 195 /** 196 * Deactivate the CS by driving it HIGH 197 * 198 * @param slave Pointer to spi_slave to which controller has to 199 * communicate with 200 */ 201 static void spi_cs_deactivate(struct udevice *dev) 202 { 203 struct udevice *bus = dev->parent; 204 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 205 struct tegra114_spi_priv *priv = dev_get_priv(bus); 206 207 setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); 208 209 /* Remember time of this transaction so we can honour the bus delay */ 210 if (pdata->deactivate_delay_us) 211 priv->last_transaction_us = timer_get_us(); 212 213 debug("Deactivate CS, bus '%s'\n", bus->name); 214 } 215 216 static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen, 217 const void *data_out, void *data_in, 218 unsigned long flags) 219 { 220 struct udevice *bus = dev->parent; 221 struct tegra114_spi_priv *priv = dev_get_priv(bus); 222 struct spi_regs *regs = priv->regs; 223 u32 reg, tmpdout, tmpdin = 0; 224 const u8 *dout = data_out; 225 u8 *din = data_in; 226 int num_bytes; 227 int ret; 228 229 debug("%s: slave %u:%u dout %p din %p bitlen %u\n", 230 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); 231 if (bitlen % 8) 232 return -1; 233 num_bytes = bitlen / 8; 234 235 ret = 0; 236 237 if (flags & SPI_XFER_BEGIN) 238 spi_cs_activate(dev); 239 240 /* clear all error status bits */ 241 reg = readl(®s->fifo_status); 242 writel(reg, ®s->fifo_status); 243 244 clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL, 245 SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE | 246 (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT)); 247 248 /* set xfer size to 1 block (32 bits) */ 249 writel(0, ®s->dma_blk); 250 251 /* handle data in 32-bit chunks */ 252 while (num_bytes > 0) { 253 int bytes; 254 int tm, i; 255 256 tmpdout = 0; 257 bytes = (num_bytes > 4) ? 4 : num_bytes; 258 259 if (dout != NULL) { 260 for (i = 0; i < bytes; ++i) 261 tmpdout = (tmpdout << 8) | dout[i]; 262 dout += bytes; 263 } 264 265 num_bytes -= bytes; 266 267 /* clear ready bit */ 268 setbits_le32(®s->xfer_status, SPI_XFER_STS_RDY); 269 270 clrsetbits_le32(®s->command1, 271 SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT, 272 (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT); 273 writel(tmpdout, ®s->tx_fifo); 274 setbits_le32(®s->command1, SPI_CMD1_GO); 275 276 /* 277 * Wait for SPI transmit FIFO to empty, or to time out. 278 * The RX FIFO status will be read and cleared last 279 */ 280 for (tm = 0; tm < SPI_TIMEOUT; ++tm) { 281 u32 fifo_status, xfer_status; 282 283 xfer_status = readl(®s->xfer_status); 284 if (!(xfer_status & SPI_XFER_STS_RDY)) 285 continue; 286 287 fifo_status = readl(®s->fifo_status); 288 if (fifo_status & SPI_FIFO_STS_ERR) { 289 debug("%s: got a fifo error: ", __func__); 290 if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF) 291 debug("tx FIFO overflow "); 292 if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR) 293 debug("tx FIFO underrun "); 294 if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF) 295 debug("rx FIFO overflow "); 296 if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR) 297 debug("rx FIFO underrun "); 298 if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL) 299 debug("tx FIFO full "); 300 if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY) 301 debug("tx FIFO empty "); 302 if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL) 303 debug("rx FIFO full "); 304 if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY) 305 debug("rx FIFO empty "); 306 debug("\n"); 307 break; 308 } 309 310 if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) { 311 tmpdin = readl(®s->rx_fifo); 312 313 /* swap bytes read in */ 314 if (din != NULL) { 315 for (i = bytes - 1; i >= 0; --i) { 316 din[i] = tmpdin & 0xff; 317 tmpdin >>= 8; 318 } 319 din += bytes; 320 } 321 322 /* We can exit when we've had both RX and TX */ 323 break; 324 } 325 } 326 327 if (tm >= SPI_TIMEOUT) 328 ret = tm; 329 330 /* clear ACK RDY, etc. bits */ 331 writel(readl(®s->fifo_status), ®s->fifo_status); 332 } 333 334 if (flags & SPI_XFER_END) 335 spi_cs_deactivate(dev); 336 337 debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", 338 __func__, tmpdin, readl(®s->fifo_status)); 339 340 if (ret) { 341 printf("%s: timeout during SPI transfer, tm %d\n", 342 __func__, ret); 343 return -1; 344 } 345 346 return ret; 347 } 348 349 static int tegra114_spi_set_speed(struct udevice *bus, uint speed) 350 { 351 struct tegra_spi_platdata *plat = bus->platdata; 352 struct tegra114_spi_priv *priv = dev_get_priv(bus); 353 354 if (speed > plat->frequency) 355 speed = plat->frequency; 356 priv->freq = speed; 357 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); 358 359 return 0; 360 } 361 362 static int tegra114_spi_set_mode(struct udevice *bus, uint mode) 363 { 364 struct tegra114_spi_priv *priv = dev_get_priv(bus); 365 366 priv->mode = mode; 367 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); 368 369 return 0; 370 } 371 372 static const struct dm_spi_ops tegra114_spi_ops = { 373 .xfer = tegra114_spi_xfer, 374 .set_speed = tegra114_spi_set_speed, 375 .set_mode = tegra114_spi_set_mode, 376 /* 377 * cs_info is not needed, since we require all chip selects to be 378 * in the device tree explicitly 379 */ 380 }; 381 382 static const struct udevice_id tegra114_spi_ids[] = { 383 { .compatible = "nvidia,tegra114-spi" }, 384 { } 385 }; 386 387 U_BOOT_DRIVER(tegra114_spi) = { 388 .name = "tegra114_spi", 389 .id = UCLASS_SPI, 390 .of_match = tegra114_spi_ids, 391 .ops = &tegra114_spi_ops, 392 .ofdata_to_platdata = tegra114_spi_ofdata_to_platdata, 393 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), 394 .priv_auto_alloc_size = sizeof(struct tegra114_spi_priv), 395 .probe = tegra114_spi_probe, 396 }; 397