1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2016 4 * 5 * Michael Kurz, <michi.kurz@gmail.com> 6 * 7 * STM32 QSPI driver 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <spi.h> 13 #include <spi_flash.h> 14 #include <asm/io.h> 15 #include <dm.h> 16 #include <errno.h> 17 #include <asm/arch/stm32.h> 18 #include <clk.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 struct stm32_qspi_regs { 23 u32 cr; /* 0x00 */ 24 u32 dcr; /* 0x04 */ 25 u32 sr; /* 0x08 */ 26 u32 fcr; /* 0x0C */ 27 u32 dlr; /* 0x10 */ 28 u32 ccr; /* 0x14 */ 29 u32 ar; /* 0x18 */ 30 u32 abr; /* 0x1C */ 31 u32 dr; /* 0x20 */ 32 u32 psmkr; /* 0x24 */ 33 u32 psmar; /* 0x28 */ 34 u32 pir; /* 0x2C */ 35 u32 lptr; /* 0x30 */ 36 }; 37 38 /* 39 * QUADSPI control register 40 */ 41 #define STM32_QSPI_CR_EN BIT(0) 42 #define STM32_QSPI_CR_ABORT BIT(1) 43 #define STM32_QSPI_CR_DMAEN BIT(2) 44 #define STM32_QSPI_CR_TCEN BIT(3) 45 #define STM32_QSPI_CR_SSHIFT BIT(4) 46 #define STM32_QSPI_CR_DFM BIT(6) 47 #define STM32_QSPI_CR_FSEL BIT(7) 48 #define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0) 49 #define STM32_QSPI_CR_FTHRES_SHIFT (8) 50 #define STM32_QSPI_CR_TEIE BIT(16) 51 #define STM32_QSPI_CR_TCIE BIT(17) 52 #define STM32_QSPI_CR_FTIE BIT(18) 53 #define STM32_QSPI_CR_SMIE BIT(19) 54 #define STM32_QSPI_CR_TOIE BIT(20) 55 #define STM32_QSPI_CR_APMS BIT(22) 56 #define STM32_QSPI_CR_PMM BIT(23) 57 #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0) 58 #define STM32_QSPI_CR_PRESCALER_SHIFT (24) 59 60 /* 61 * QUADSPI device configuration register 62 */ 63 #define STM32_QSPI_DCR_CKMODE BIT(0) 64 #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0) 65 #define STM32_QSPI_DCR_CSHT_SHIFT (8) 66 #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0) 67 #define STM32_QSPI_DCR_FSIZE_SHIFT (16) 68 69 /* 70 * QUADSPI status register 71 */ 72 #define STM32_QSPI_SR_TEF BIT(0) 73 #define STM32_QSPI_SR_TCF BIT(1) 74 #define STM32_QSPI_SR_FTF BIT(2) 75 #define STM32_QSPI_SR_SMF BIT(3) 76 #define STM32_QSPI_SR_TOF BIT(4) 77 #define STM32_QSPI_SR_BUSY BIT(5) 78 #define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0) 79 #define STM32_QSPI_SR_FLEVEL_SHIFT (8) 80 81 /* 82 * QUADSPI flag clear register 83 */ 84 #define STM32_QSPI_FCR_CTEF BIT(0) 85 #define STM32_QSPI_FCR_CTCF BIT(1) 86 #define STM32_QSPI_FCR_CSMF BIT(3) 87 #define STM32_QSPI_FCR_CTOF BIT(4) 88 89 /* 90 * QUADSPI communication configuration register 91 */ 92 #define STM32_QSPI_CCR_DDRM BIT(31) 93 #define STM32_QSPI_CCR_DHHC BIT(30) 94 #define STM32_QSPI_CCR_SIOO BIT(28) 95 #define STM32_QSPI_CCR_FMODE_SHIFT (26) 96 #define STM32_QSPI_CCR_DMODE_SHIFT (24) 97 #define STM32_QSPI_CCR_DCYC_SHIFT (18) 98 #define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0) 99 #define STM32_QSPI_CCR_ABSIZE_SHIFT (16) 100 #define STM32_QSPI_CCR_ABMODE_SHIFT (14) 101 #define STM32_QSPI_CCR_ADSIZE_SHIFT (12) 102 #define STM32_QSPI_CCR_ADMODE_SHIFT (10) 103 #define STM32_QSPI_CCR_IMODE_SHIFT (8) 104 #define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0) 105 106 enum STM32_QSPI_CCR_IMODE { 107 STM32_QSPI_CCR_IMODE_NONE = 0, 108 STM32_QSPI_CCR_IMODE_ONE_LINE = 1, 109 STM32_QSPI_CCR_IMODE_TWO_LINE = 2, 110 STM32_QSPI_CCR_IMODE_FOUR_LINE = 3, 111 }; 112 113 enum STM32_QSPI_CCR_ADMODE { 114 STM32_QSPI_CCR_ADMODE_NONE = 0, 115 STM32_QSPI_CCR_ADMODE_ONE_LINE = 1, 116 STM32_QSPI_CCR_ADMODE_TWO_LINE = 2, 117 STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3, 118 }; 119 120 enum STM32_QSPI_CCR_ADSIZE { 121 STM32_QSPI_CCR_ADSIZE_8BIT = 0, 122 STM32_QSPI_CCR_ADSIZE_16BIT = 1, 123 STM32_QSPI_CCR_ADSIZE_24BIT = 2, 124 STM32_QSPI_CCR_ADSIZE_32BIT = 3, 125 }; 126 127 enum STM32_QSPI_CCR_ABMODE { 128 STM32_QSPI_CCR_ABMODE_NONE = 0, 129 STM32_QSPI_CCR_ABMODE_ONE_LINE = 1, 130 STM32_QSPI_CCR_ABMODE_TWO_LINE = 2, 131 STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3, 132 }; 133 134 enum STM32_QSPI_CCR_ABSIZE { 135 STM32_QSPI_CCR_ABSIZE_8BIT = 0, 136 STM32_QSPI_CCR_ABSIZE_16BIT = 1, 137 STM32_QSPI_CCR_ABSIZE_24BIT = 2, 138 STM32_QSPI_CCR_ABSIZE_32BIT = 3, 139 }; 140 141 enum STM32_QSPI_CCR_DMODE { 142 STM32_QSPI_CCR_DMODE_NONE = 0, 143 STM32_QSPI_CCR_DMODE_ONE_LINE = 1, 144 STM32_QSPI_CCR_DMODE_TWO_LINE = 2, 145 STM32_QSPI_CCR_DMODE_FOUR_LINE = 3, 146 }; 147 148 enum STM32_QSPI_CCR_FMODE { 149 STM32_QSPI_CCR_IND_WRITE = 0, 150 STM32_QSPI_CCR_IND_READ = 1, 151 STM32_QSPI_CCR_AUTO_POLL = 2, 152 STM32_QSPI_CCR_MEM_MAP = 3, 153 }; 154 155 /* default SCK frequency, unit: HZ */ 156 #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000 157 158 struct stm32_qspi_platdata { 159 u32 base; 160 u32 memory_map; 161 u32 max_hz; 162 }; 163 164 struct stm32_qspi_priv { 165 struct stm32_qspi_regs *regs; 166 ulong clock_rate; 167 u32 max_hz; 168 u32 mode; 169 170 u32 command; 171 u32 address; 172 u32 dummycycles; 173 #define CMD_HAS_ADR BIT(24) 174 #define CMD_HAS_DUMMY BIT(25) 175 #define CMD_HAS_DATA BIT(26) 176 }; 177 178 static void _stm32_qspi_disable(struct stm32_qspi_priv *priv) 179 { 180 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN); 181 } 182 183 static void _stm32_qspi_enable(struct stm32_qspi_priv *priv) 184 { 185 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN); 186 } 187 188 static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv) 189 { 190 while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY) 191 ; 192 } 193 194 static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv) 195 { 196 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF)) 197 ; 198 } 199 200 static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv) 201 { 202 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF)) 203 ; 204 } 205 206 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size) 207 { 208 u32 fsize = fls(size) - 1; 209 clrsetbits_le32(&priv->regs->dcr, 210 STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT, 211 fsize << STM32_QSPI_DCR_FSIZE_SHIFT); 212 } 213 214 static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv) 215 { 216 unsigned int ccr_reg = 0; 217 u8 imode, admode, dmode; 218 u32 mode = priv->mode; 219 u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK); 220 221 imode = STM32_QSPI_CCR_IMODE_ONE_LINE; 222 admode = STM32_QSPI_CCR_ADMODE_ONE_LINE; 223 224 if (mode & SPI_RX_QUAD) { 225 dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE; 226 if (mode & SPI_TX_QUAD) { 227 imode = STM32_QSPI_CCR_IMODE_FOUR_LINE; 228 admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE; 229 } 230 } else if (mode & SPI_RX_DUAL) { 231 dmode = STM32_QSPI_CCR_DMODE_TWO_LINE; 232 if (mode & SPI_TX_DUAL) { 233 imode = STM32_QSPI_CCR_IMODE_TWO_LINE; 234 admode = STM32_QSPI_CCR_ADMODE_TWO_LINE; 235 } 236 } else { 237 dmode = STM32_QSPI_CCR_DMODE_ONE_LINE; 238 } 239 240 if (priv->command & CMD_HAS_DATA) 241 ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT); 242 243 if (priv->command & CMD_HAS_DUMMY) 244 ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK) 245 << STM32_QSPI_CCR_DCYC_SHIFT); 246 247 if (priv->command & CMD_HAS_ADR) { 248 ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT 249 << STM32_QSPI_CCR_ADSIZE_SHIFT); 250 ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT); 251 } 252 ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT); 253 ccr_reg |= cmd; 254 return ccr_reg; 255 } 256 257 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv, 258 struct spi_flash *flash) 259 { 260 priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA 261 | CMD_HAS_DUMMY; 262 priv->dummycycles = flash->dummy_byte * 8; 263 264 unsigned int ccr_reg = _stm32_qspi_gen_ccr(priv); 265 ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT); 266 267 _stm32_qspi_wait_for_not_busy(priv); 268 269 writel(ccr_reg, &priv->regs->ccr); 270 271 priv->dummycycles = 0; 272 } 273 274 static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv) 275 { 276 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT); 277 } 278 279 static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv, 280 u32 length) 281 { 282 writel(length - 1, &priv->regs->dlr); 283 } 284 285 static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg) 286 { 287 writel(cr_reg, &priv->regs->ccr); 288 289 if (priv->command & CMD_HAS_ADR) 290 writel(priv->address, &priv->regs->ar); 291 } 292 293 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv, 294 struct spi_flash *flash, unsigned int bitlen, 295 const u8 *dout, u8 *din, unsigned long flags) 296 { 297 unsigned int words = bitlen / 8; 298 299 if (flags & SPI_XFER_MMAP) { 300 _stm32_qspi_enable_mmap(priv, flash); 301 return 0; 302 } else if (flags & SPI_XFER_MMAP_END) { 303 _stm32_qspi_disable_mmap(priv); 304 return 0; 305 } 306 307 if (bitlen == 0) 308 return -1; 309 310 if (bitlen % 8) { 311 debug("spi_xfer: Non byte aligned SPI transfer\n"); 312 return -1; 313 } 314 315 if (dout && din) { 316 debug("spi_xfer: QSPI cannot have data in and data out set\n"); 317 return -1; 318 } 319 320 if (!dout && (flags & SPI_XFER_BEGIN)) { 321 debug("spi_xfer: QSPI transfer must begin with command\n"); 322 return -1; 323 } 324 325 if (dout) { 326 if (flags & SPI_XFER_BEGIN) { 327 /* data is command */ 328 priv->command = dout[0] | CMD_HAS_DATA; 329 if (words >= 4) { 330 /* address is here too */ 331 priv->address = (dout[1] << 16) | 332 (dout[2] << 8) | dout[3]; 333 priv->command |= CMD_HAS_ADR; 334 } 335 336 if (words > 4) { 337 /* rest is dummy bytes */ 338 priv->dummycycles = (words - 4) * 8; 339 priv->command |= CMD_HAS_DUMMY; 340 } 341 342 if (flags & SPI_XFER_END) { 343 /* command without data */ 344 priv->command &= ~(CMD_HAS_DATA); 345 } 346 } 347 348 if (flags & SPI_XFER_END) { 349 u32 ccr_reg = _stm32_qspi_gen_ccr(priv); 350 ccr_reg |= STM32_QSPI_CCR_IND_WRITE 351 << STM32_QSPI_CCR_FMODE_SHIFT; 352 353 _stm32_qspi_wait_for_not_busy(priv); 354 355 if (priv->command & CMD_HAS_DATA) 356 _stm32_qspi_set_xfer_length(priv, words); 357 358 _stm32_qspi_start_xfer(priv, ccr_reg); 359 360 debug("%s: write: ccr:0x%08x adr:0x%08x\n", 361 __func__, priv->regs->ccr, priv->regs->ar); 362 363 if (priv->command & CMD_HAS_DATA) { 364 _stm32_qspi_wait_for_ftf(priv); 365 366 debug("%s: words:%d data:", __func__, words); 367 368 int i = 0; 369 while (words > i) { 370 writeb(dout[i], &priv->regs->dr); 371 debug("%02x ", dout[i]); 372 i++; 373 } 374 debug("\n"); 375 376 _stm32_qspi_wait_for_complete(priv); 377 } else { 378 _stm32_qspi_wait_for_not_busy(priv); 379 } 380 } 381 } else if (din) { 382 u32 ccr_reg = _stm32_qspi_gen_ccr(priv); 383 ccr_reg |= STM32_QSPI_CCR_IND_READ 384 << STM32_QSPI_CCR_FMODE_SHIFT; 385 386 _stm32_qspi_wait_for_not_busy(priv); 387 388 _stm32_qspi_set_xfer_length(priv, words); 389 390 _stm32_qspi_start_xfer(priv, ccr_reg); 391 392 debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__, 393 priv->regs->ccr, priv->regs->ar, priv->regs->dlr); 394 395 debug("%s: data:", __func__); 396 397 int i = 0; 398 while (words > i) { 399 din[i] = readb(&priv->regs->dr); 400 debug("%02x ", din[i]); 401 i++; 402 } 403 debug("\n"); 404 } 405 406 return 0; 407 } 408 409 static int stm32_qspi_ofdata_to_platdata(struct udevice *bus) 410 { 411 struct fdt_resource res_regs, res_mem; 412 struct stm32_qspi_platdata *plat = bus->platdata; 413 const void *blob = gd->fdt_blob; 414 int node = dev_of_offset(bus); 415 int ret; 416 417 ret = fdt_get_named_resource(blob, node, "reg", "reg-names", 418 "QuadSPI", &res_regs); 419 if (ret) { 420 debug("Error: can't get regs base addresses(ret = %d)!\n", ret); 421 return -ENOMEM; 422 } 423 ret = fdt_get_named_resource(blob, node, "reg", "reg-names", 424 "QuadSPI-memory", &res_mem); 425 if (ret) { 426 debug("Error: can't get mmap base address(ret = %d)!\n", ret); 427 return -ENOMEM; 428 } 429 430 plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 431 STM32_QSPI_DEFAULT_SCK_FREQ); 432 433 plat->base = res_regs.start; 434 plat->memory_map = res_mem.start; 435 436 debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n", 437 __func__, 438 plat->base, 439 plat->memory_map, 440 plat->max_hz 441 ); 442 443 return 0; 444 } 445 446 static int stm32_qspi_probe(struct udevice *bus) 447 { 448 struct stm32_qspi_platdata *plat = dev_get_platdata(bus); 449 struct stm32_qspi_priv *priv = dev_get_priv(bus); 450 struct dm_spi_bus *dm_spi_bus; 451 452 dm_spi_bus = bus->uclass_priv; 453 454 dm_spi_bus->max_hz = plat->max_hz; 455 456 priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base; 457 458 priv->max_hz = plat->max_hz; 459 460 #ifdef CONFIG_CLK 461 int ret; 462 struct clk clk; 463 ret = clk_get_by_index(bus, 0, &clk); 464 if (ret < 0) 465 return ret; 466 467 ret = clk_enable(&clk); 468 469 if (ret) { 470 dev_err(bus, "failed to enable clock\n"); 471 return ret; 472 } 473 474 priv->clock_rate = clk_get_rate(&clk); 475 if (priv->clock_rate < 0) { 476 clk_disable(&clk); 477 return priv->clock_rate; 478 } 479 480 #endif 481 482 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT); 483 484 return 0; 485 } 486 487 static int stm32_qspi_remove(struct udevice *bus) 488 { 489 return 0; 490 } 491 492 static int stm32_qspi_claim_bus(struct udevice *dev) 493 { 494 struct stm32_qspi_priv *priv; 495 struct udevice *bus; 496 struct spi_flash *flash; 497 498 bus = dev->parent; 499 priv = dev_get_priv(bus); 500 flash = dev_get_uclass_priv(dev); 501 502 _stm32_qspi_set_flash_size(priv, flash->size); 503 504 _stm32_qspi_enable(priv); 505 506 return 0; 507 } 508 509 static int stm32_qspi_release_bus(struct udevice *dev) 510 { 511 struct stm32_qspi_priv *priv; 512 struct udevice *bus; 513 514 bus = dev->parent; 515 priv = dev_get_priv(bus); 516 517 _stm32_qspi_disable(priv); 518 519 return 0; 520 } 521 522 static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen, 523 const void *dout, void *din, unsigned long flags) 524 { 525 struct stm32_qspi_priv *priv; 526 struct udevice *bus; 527 struct spi_flash *flash; 528 529 bus = dev->parent; 530 priv = dev_get_priv(bus); 531 flash = dev_get_uclass_priv(dev); 532 533 return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout, 534 (u8 *)din, flags); 535 } 536 537 static int stm32_qspi_set_speed(struct udevice *bus, uint speed) 538 { 539 struct stm32_qspi_platdata *plat = bus->platdata; 540 struct stm32_qspi_priv *priv = dev_get_priv(bus); 541 542 if (speed > plat->max_hz) 543 speed = plat->max_hz; 544 545 u32 qspi_clk = priv->clock_rate; 546 u32 prescaler = 255; 547 if (speed > 0) { 548 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1; 549 if (prescaler > 255) 550 prescaler = 255; 551 else if (prescaler < 0) 552 prescaler = 0; 553 } 554 555 u32 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000); 556 csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK; 557 558 _stm32_qspi_wait_for_not_busy(priv); 559 560 clrsetbits_le32(&priv->regs->cr, 561 STM32_QSPI_CR_PRESCALER_MASK << 562 STM32_QSPI_CR_PRESCALER_SHIFT, 563 prescaler << STM32_QSPI_CR_PRESCALER_SHIFT); 564 565 566 clrsetbits_le32(&priv->regs->dcr, 567 STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT, 568 csht << STM32_QSPI_DCR_CSHT_SHIFT); 569 570 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, 571 (qspi_clk / (prescaler + 1))); 572 573 return 0; 574 } 575 576 static int stm32_qspi_set_mode(struct udevice *bus, uint mode) 577 { 578 struct stm32_qspi_priv *priv = dev_get_priv(bus); 579 580 _stm32_qspi_wait_for_not_busy(priv); 581 582 if ((mode & SPI_CPHA) && (mode & SPI_CPOL)) 583 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); 584 else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL)) 585 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); 586 else 587 return -ENODEV; 588 589 if (mode & SPI_CS_HIGH) 590 return -ENODEV; 591 592 if (mode & SPI_RX_QUAD) 593 priv->mode |= SPI_RX_QUAD; 594 else if (mode & SPI_RX_DUAL) 595 priv->mode |= SPI_RX_DUAL; 596 else 597 priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL); 598 599 if (mode & SPI_TX_QUAD) 600 priv->mode |= SPI_TX_QUAD; 601 else if (mode & SPI_TX_DUAL) 602 priv->mode |= SPI_TX_DUAL; 603 else 604 priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL); 605 606 debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode); 607 608 if (mode & SPI_RX_QUAD) 609 debug("quad, tx: "); 610 else if (mode & SPI_RX_DUAL) 611 debug("dual, tx: "); 612 else 613 debug("single, tx: "); 614 615 if (mode & SPI_TX_QUAD) 616 debug("quad\n"); 617 else if (mode & SPI_TX_DUAL) 618 debug("dual\n"); 619 else 620 debug("single\n"); 621 622 return 0; 623 } 624 625 static const struct dm_spi_ops stm32_qspi_ops = { 626 .claim_bus = stm32_qspi_claim_bus, 627 .release_bus = stm32_qspi_release_bus, 628 .xfer = stm32_qspi_xfer, 629 .set_speed = stm32_qspi_set_speed, 630 .set_mode = stm32_qspi_set_mode, 631 }; 632 633 static const struct udevice_id stm32_qspi_ids[] = { 634 { .compatible = "st,stm32-qspi" }, 635 { } 636 }; 637 638 U_BOOT_DRIVER(stm32_qspi) = { 639 .name = "stm32_qspi", 640 .id = UCLASS_SPI, 641 .of_match = stm32_qspi_ids, 642 .ops = &stm32_qspi_ops, 643 .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata, 644 .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata), 645 .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv), 646 .probe = stm32_qspi_probe, 647 .remove = stm32_qspi_remove, 648 }; 649