1 /* 2 * (C) Copyright 2016 3 * 4 * Michael Kurz, <michi.kurz@gmail.com> 5 * 6 * STM32 QSPI driver 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <spi.h> 14 #include <spi_flash.h> 15 #include <asm/io.h> 16 #include <dm.h> 17 #include <errno.h> 18 #include <asm/arch/stm32.h> 19 #include <clk.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 struct stm32_qspi_regs { 24 u32 cr; /* 0x00 */ 25 u32 dcr; /* 0x04 */ 26 u32 sr; /* 0x08 */ 27 u32 fcr; /* 0x0C */ 28 u32 dlr; /* 0x10 */ 29 u32 ccr; /* 0x14 */ 30 u32 ar; /* 0x18 */ 31 u32 abr; /* 0x1C */ 32 u32 dr; /* 0x20 */ 33 u32 psmkr; /* 0x24 */ 34 u32 psmar; /* 0x28 */ 35 u32 pir; /* 0x2C */ 36 u32 lptr; /* 0x30 */ 37 }; 38 39 /* 40 * QUADSPI control register 41 */ 42 #define STM32_QSPI_CR_EN BIT(0) 43 #define STM32_QSPI_CR_ABORT BIT(1) 44 #define STM32_QSPI_CR_DMAEN BIT(2) 45 #define STM32_QSPI_CR_TCEN BIT(3) 46 #define STM32_QSPI_CR_SSHIFT BIT(4) 47 #define STM32_QSPI_CR_DFM BIT(6) 48 #define STM32_QSPI_CR_FSEL BIT(7) 49 #define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0) 50 #define STM32_QSPI_CR_FTHRES_SHIFT (8) 51 #define STM32_QSPI_CR_TEIE BIT(16) 52 #define STM32_QSPI_CR_TCIE BIT(17) 53 #define STM32_QSPI_CR_FTIE BIT(18) 54 #define STM32_QSPI_CR_SMIE BIT(19) 55 #define STM32_QSPI_CR_TOIE BIT(20) 56 #define STM32_QSPI_CR_APMS BIT(22) 57 #define STM32_QSPI_CR_PMM BIT(23) 58 #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0) 59 #define STM32_QSPI_CR_PRESCALER_SHIFT (24) 60 61 /* 62 * QUADSPI device configuration register 63 */ 64 #define STM32_QSPI_DCR_CKMODE BIT(0) 65 #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0) 66 #define STM32_QSPI_DCR_CSHT_SHIFT (8) 67 #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0) 68 #define STM32_QSPI_DCR_FSIZE_SHIFT (16) 69 70 /* 71 * QUADSPI status register 72 */ 73 #define STM32_QSPI_SR_TEF BIT(0) 74 #define STM32_QSPI_SR_TCF BIT(1) 75 #define STM32_QSPI_SR_FTF BIT(2) 76 #define STM32_QSPI_SR_SMF BIT(3) 77 #define STM32_QSPI_SR_TOF BIT(4) 78 #define STM32_QSPI_SR_BUSY BIT(5) 79 #define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0) 80 #define STM32_QSPI_SR_FLEVEL_SHIFT (8) 81 82 /* 83 * QUADSPI flag clear register 84 */ 85 #define STM32_QSPI_FCR_CTEF BIT(0) 86 #define STM32_QSPI_FCR_CTCF BIT(1) 87 #define STM32_QSPI_FCR_CSMF BIT(3) 88 #define STM32_QSPI_FCR_CTOF BIT(4) 89 90 /* 91 * QUADSPI communication configuration register 92 */ 93 #define STM32_QSPI_CCR_DDRM BIT(31) 94 #define STM32_QSPI_CCR_DHHC BIT(30) 95 #define STM32_QSPI_CCR_SIOO BIT(28) 96 #define STM32_QSPI_CCR_FMODE_SHIFT (26) 97 #define STM32_QSPI_CCR_DMODE_SHIFT (24) 98 #define STM32_QSPI_CCR_DCYC_SHIFT (18) 99 #define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0) 100 #define STM32_QSPI_CCR_ABSIZE_SHIFT (16) 101 #define STM32_QSPI_CCR_ABMODE_SHIFT (14) 102 #define STM32_QSPI_CCR_ADSIZE_SHIFT (12) 103 #define STM32_QSPI_CCR_ADMODE_SHIFT (10) 104 #define STM32_QSPI_CCR_IMODE_SHIFT (8) 105 #define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0) 106 107 enum STM32_QSPI_CCR_IMODE { 108 STM32_QSPI_CCR_IMODE_NONE = 0, 109 STM32_QSPI_CCR_IMODE_ONE_LINE = 1, 110 STM32_QSPI_CCR_IMODE_TWO_LINE = 2, 111 STM32_QSPI_CCR_IMODE_FOUR_LINE = 3, 112 }; 113 114 enum STM32_QSPI_CCR_ADMODE { 115 STM32_QSPI_CCR_ADMODE_NONE = 0, 116 STM32_QSPI_CCR_ADMODE_ONE_LINE = 1, 117 STM32_QSPI_CCR_ADMODE_TWO_LINE = 2, 118 STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3, 119 }; 120 121 enum STM32_QSPI_CCR_ADSIZE { 122 STM32_QSPI_CCR_ADSIZE_8BIT = 0, 123 STM32_QSPI_CCR_ADSIZE_16BIT = 1, 124 STM32_QSPI_CCR_ADSIZE_24BIT = 2, 125 STM32_QSPI_CCR_ADSIZE_32BIT = 3, 126 }; 127 128 enum STM32_QSPI_CCR_ABMODE { 129 STM32_QSPI_CCR_ABMODE_NONE = 0, 130 STM32_QSPI_CCR_ABMODE_ONE_LINE = 1, 131 STM32_QSPI_CCR_ABMODE_TWO_LINE = 2, 132 STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3, 133 }; 134 135 enum STM32_QSPI_CCR_ABSIZE { 136 STM32_QSPI_CCR_ABSIZE_8BIT = 0, 137 STM32_QSPI_CCR_ABSIZE_16BIT = 1, 138 STM32_QSPI_CCR_ABSIZE_24BIT = 2, 139 STM32_QSPI_CCR_ABSIZE_32BIT = 3, 140 }; 141 142 enum STM32_QSPI_CCR_DMODE { 143 STM32_QSPI_CCR_DMODE_NONE = 0, 144 STM32_QSPI_CCR_DMODE_ONE_LINE = 1, 145 STM32_QSPI_CCR_DMODE_TWO_LINE = 2, 146 STM32_QSPI_CCR_DMODE_FOUR_LINE = 3, 147 }; 148 149 enum STM32_QSPI_CCR_FMODE { 150 STM32_QSPI_CCR_IND_WRITE = 0, 151 STM32_QSPI_CCR_IND_READ = 1, 152 STM32_QSPI_CCR_AUTO_POLL = 2, 153 STM32_QSPI_CCR_MEM_MAP = 3, 154 }; 155 156 /* default SCK frequency, unit: HZ */ 157 #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000 158 159 struct stm32_qspi_platdata { 160 u32 base; 161 u32 memory_map; 162 u32 max_hz; 163 }; 164 165 struct stm32_qspi_priv { 166 struct stm32_qspi_regs *regs; 167 ulong clock_rate; 168 u32 max_hz; 169 u32 mode; 170 171 u32 command; 172 u32 address; 173 u32 dummycycles; 174 #define CMD_HAS_ADR BIT(24) 175 #define CMD_HAS_DUMMY BIT(25) 176 #define CMD_HAS_DATA BIT(26) 177 }; 178 179 static void _stm32_qspi_disable(struct stm32_qspi_priv *priv) 180 { 181 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN); 182 } 183 184 static void _stm32_qspi_enable(struct stm32_qspi_priv *priv) 185 { 186 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN); 187 } 188 189 static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv) 190 { 191 while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY) 192 ; 193 } 194 195 static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv) 196 { 197 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF)) 198 ; 199 } 200 201 static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv) 202 { 203 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF)) 204 ; 205 } 206 207 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size) 208 { 209 u32 fsize = fls(size) - 1; 210 clrsetbits_le32(&priv->regs->dcr, 211 STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT, 212 fsize << STM32_QSPI_DCR_FSIZE_SHIFT); 213 } 214 215 static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv) 216 { 217 unsigned int ccr_reg = 0; 218 u8 imode, admode, dmode; 219 u32 mode = priv->mode; 220 u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK); 221 222 imode = STM32_QSPI_CCR_IMODE_ONE_LINE; 223 admode = STM32_QSPI_CCR_ADMODE_ONE_LINE; 224 225 if (mode & SPI_RX_QUAD) { 226 dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE; 227 if (mode & SPI_TX_QUAD) { 228 imode = STM32_QSPI_CCR_IMODE_FOUR_LINE; 229 admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE; 230 } 231 } else if (mode & SPI_RX_DUAL) { 232 dmode = STM32_QSPI_CCR_DMODE_TWO_LINE; 233 if (mode & SPI_TX_DUAL) { 234 imode = STM32_QSPI_CCR_IMODE_TWO_LINE; 235 admode = STM32_QSPI_CCR_ADMODE_TWO_LINE; 236 } 237 } else { 238 dmode = STM32_QSPI_CCR_DMODE_ONE_LINE; 239 } 240 241 if (priv->command & CMD_HAS_DATA) 242 ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT); 243 244 if (priv->command & CMD_HAS_DUMMY) 245 ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK) 246 << STM32_QSPI_CCR_DCYC_SHIFT); 247 248 if (priv->command & CMD_HAS_ADR) { 249 ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT 250 << STM32_QSPI_CCR_ADSIZE_SHIFT); 251 ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT); 252 } 253 ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT); 254 ccr_reg |= cmd; 255 return ccr_reg; 256 } 257 258 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv, 259 struct spi_flash *flash) 260 { 261 priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA 262 | CMD_HAS_DUMMY; 263 priv->dummycycles = flash->dummy_byte * 8; 264 265 unsigned int ccr_reg = _stm32_qspi_gen_ccr(priv); 266 ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT); 267 268 _stm32_qspi_wait_for_not_busy(priv); 269 270 writel(ccr_reg, &priv->regs->ccr); 271 272 priv->dummycycles = 0; 273 } 274 275 static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv) 276 { 277 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT); 278 } 279 280 static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv, 281 u32 length) 282 { 283 writel(length - 1, &priv->regs->dlr); 284 } 285 286 static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg) 287 { 288 writel(cr_reg, &priv->regs->ccr); 289 290 if (priv->command & CMD_HAS_ADR) 291 writel(priv->address, &priv->regs->ar); 292 } 293 294 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv, 295 struct spi_flash *flash, unsigned int bitlen, 296 const u8 *dout, u8 *din, unsigned long flags) 297 { 298 unsigned int words = bitlen / 8; 299 300 if (flags & SPI_XFER_MMAP) { 301 _stm32_qspi_enable_mmap(priv, flash); 302 return 0; 303 } else if (flags & SPI_XFER_MMAP_END) { 304 _stm32_qspi_disable_mmap(priv); 305 return 0; 306 } 307 308 if (bitlen == 0) 309 return -1; 310 311 if (bitlen % 8) { 312 debug("spi_xfer: Non byte aligned SPI transfer\n"); 313 return -1; 314 } 315 316 if (dout && din) { 317 debug("spi_xfer: QSPI cannot have data in and data out set\n"); 318 return -1; 319 } 320 321 if (!dout && (flags & SPI_XFER_BEGIN)) { 322 debug("spi_xfer: QSPI transfer must begin with command\n"); 323 return -1; 324 } 325 326 if (dout) { 327 if (flags & SPI_XFER_BEGIN) { 328 /* data is command */ 329 priv->command = dout[0] | CMD_HAS_DATA; 330 if (words >= 4) { 331 /* address is here too */ 332 priv->address = (dout[1] << 16) | 333 (dout[2] << 8) | dout[3]; 334 priv->command |= CMD_HAS_ADR; 335 } 336 337 if (words > 4) { 338 /* rest is dummy bytes */ 339 priv->dummycycles = (words - 4) * 8; 340 priv->command |= CMD_HAS_DUMMY; 341 } 342 343 if (flags & SPI_XFER_END) { 344 /* command without data */ 345 priv->command &= ~(CMD_HAS_DATA); 346 } 347 } 348 349 if (flags & SPI_XFER_END) { 350 u32 ccr_reg = _stm32_qspi_gen_ccr(priv); 351 ccr_reg |= STM32_QSPI_CCR_IND_WRITE 352 << STM32_QSPI_CCR_FMODE_SHIFT; 353 354 _stm32_qspi_wait_for_not_busy(priv); 355 356 if (priv->command & CMD_HAS_DATA) 357 _stm32_qspi_set_xfer_length(priv, words); 358 359 _stm32_qspi_start_xfer(priv, ccr_reg); 360 361 debug("%s: write: ccr:0x%08x adr:0x%08x\n", 362 __func__, priv->regs->ccr, priv->regs->ar); 363 364 if (priv->command & CMD_HAS_DATA) { 365 _stm32_qspi_wait_for_ftf(priv); 366 367 debug("%s: words:%d data:", __func__, words); 368 369 int i = 0; 370 while (words > i) { 371 writeb(dout[i], &priv->regs->dr); 372 debug("%02x ", dout[i]); 373 i++; 374 } 375 debug("\n"); 376 377 _stm32_qspi_wait_for_complete(priv); 378 } else { 379 _stm32_qspi_wait_for_not_busy(priv); 380 } 381 } 382 } else if (din) { 383 u32 ccr_reg = _stm32_qspi_gen_ccr(priv); 384 ccr_reg |= STM32_QSPI_CCR_IND_READ 385 << STM32_QSPI_CCR_FMODE_SHIFT; 386 387 _stm32_qspi_wait_for_not_busy(priv); 388 389 _stm32_qspi_set_xfer_length(priv, words); 390 391 _stm32_qspi_start_xfer(priv, ccr_reg); 392 393 debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__, 394 priv->regs->ccr, priv->regs->ar, priv->regs->dlr); 395 396 debug("%s: data:", __func__); 397 398 int i = 0; 399 while (words > i) { 400 din[i] = readb(&priv->regs->dr); 401 debug("%02x ", din[i]); 402 i++; 403 } 404 debug("\n"); 405 } 406 407 return 0; 408 } 409 410 static int stm32_qspi_ofdata_to_platdata(struct udevice *bus) 411 { 412 struct fdt_resource res_regs, res_mem; 413 struct stm32_qspi_platdata *plat = bus->platdata; 414 const void *blob = gd->fdt_blob; 415 int node = dev_of_offset(bus); 416 int ret; 417 418 ret = fdt_get_named_resource(blob, node, "reg", "reg-names", 419 "QuadSPI", &res_regs); 420 if (ret) { 421 debug("Error: can't get regs base addresses(ret = %d)!\n", ret); 422 return -ENOMEM; 423 } 424 ret = fdt_get_named_resource(blob, node, "reg", "reg-names", 425 "QuadSPI-memory", &res_mem); 426 if (ret) { 427 debug("Error: can't get mmap base address(ret = %d)!\n", ret); 428 return -ENOMEM; 429 } 430 431 plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 432 STM32_QSPI_DEFAULT_SCK_FREQ); 433 434 plat->base = res_regs.start; 435 plat->memory_map = res_mem.start; 436 437 debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n", 438 __func__, 439 plat->base, 440 plat->memory_map, 441 plat->max_hz 442 ); 443 444 return 0; 445 } 446 447 static int stm32_qspi_probe(struct udevice *bus) 448 { 449 struct stm32_qspi_platdata *plat = dev_get_platdata(bus); 450 struct stm32_qspi_priv *priv = dev_get_priv(bus); 451 struct dm_spi_bus *dm_spi_bus; 452 453 dm_spi_bus = bus->uclass_priv; 454 455 dm_spi_bus->max_hz = plat->max_hz; 456 457 priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base; 458 459 priv->max_hz = plat->max_hz; 460 461 #ifdef CONFIG_CLK 462 int ret; 463 struct clk clk; 464 ret = clk_get_by_index(bus, 0, &clk); 465 if (ret < 0) 466 return ret; 467 468 ret = clk_enable(&clk); 469 470 if (ret) { 471 dev_err(bus, "failed to enable clock\n"); 472 return ret; 473 } 474 475 priv->clock_rate = clk_get_rate(&clk); 476 if (priv->clock_rate < 0) { 477 clk_disable(&clk); 478 return priv->clock_rate; 479 } 480 481 #endif 482 483 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT); 484 485 return 0; 486 } 487 488 static int stm32_qspi_remove(struct udevice *bus) 489 { 490 return 0; 491 } 492 493 static int stm32_qspi_claim_bus(struct udevice *dev) 494 { 495 struct stm32_qspi_priv *priv; 496 struct udevice *bus; 497 struct spi_flash *flash; 498 499 bus = dev->parent; 500 priv = dev_get_priv(bus); 501 flash = dev_get_uclass_priv(dev); 502 503 _stm32_qspi_set_flash_size(priv, flash->size); 504 505 _stm32_qspi_enable(priv); 506 507 return 0; 508 } 509 510 static int stm32_qspi_release_bus(struct udevice *dev) 511 { 512 struct stm32_qspi_priv *priv; 513 struct udevice *bus; 514 515 bus = dev->parent; 516 priv = dev_get_priv(bus); 517 518 _stm32_qspi_disable(priv); 519 520 return 0; 521 } 522 523 static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen, 524 const void *dout, void *din, unsigned long flags) 525 { 526 struct stm32_qspi_priv *priv; 527 struct udevice *bus; 528 struct spi_flash *flash; 529 530 bus = dev->parent; 531 priv = dev_get_priv(bus); 532 flash = dev_get_uclass_priv(dev); 533 534 return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout, 535 (u8 *)din, flags); 536 } 537 538 static int stm32_qspi_set_speed(struct udevice *bus, uint speed) 539 { 540 struct stm32_qspi_platdata *plat = bus->platdata; 541 struct stm32_qspi_priv *priv = dev_get_priv(bus); 542 543 if (speed > plat->max_hz) 544 speed = plat->max_hz; 545 546 u32 qspi_clk = priv->clock_rate; 547 u32 prescaler = 255; 548 if (speed > 0) { 549 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1; 550 if (prescaler > 255) 551 prescaler = 255; 552 else if (prescaler < 0) 553 prescaler = 0; 554 } 555 556 u32 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000); 557 csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK; 558 559 _stm32_qspi_wait_for_not_busy(priv); 560 561 clrsetbits_le32(&priv->regs->cr, 562 STM32_QSPI_CR_PRESCALER_MASK << 563 STM32_QSPI_CR_PRESCALER_SHIFT, 564 prescaler << STM32_QSPI_CR_PRESCALER_SHIFT); 565 566 567 clrsetbits_le32(&priv->regs->dcr, 568 STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT, 569 csht << STM32_QSPI_DCR_CSHT_SHIFT); 570 571 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, 572 (qspi_clk / (prescaler + 1))); 573 574 return 0; 575 } 576 577 static int stm32_qspi_set_mode(struct udevice *bus, uint mode) 578 { 579 struct stm32_qspi_priv *priv = dev_get_priv(bus); 580 581 _stm32_qspi_wait_for_not_busy(priv); 582 583 if ((mode & SPI_CPHA) && (mode & SPI_CPOL)) 584 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); 585 else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL)) 586 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); 587 else 588 return -ENODEV; 589 590 if (mode & SPI_CS_HIGH) 591 return -ENODEV; 592 593 if (mode & SPI_RX_QUAD) 594 priv->mode |= SPI_RX_QUAD; 595 else if (mode & SPI_RX_DUAL) 596 priv->mode |= SPI_RX_DUAL; 597 else 598 priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL); 599 600 if (mode & SPI_TX_QUAD) 601 priv->mode |= SPI_TX_QUAD; 602 else if (mode & SPI_TX_DUAL) 603 priv->mode |= SPI_TX_DUAL; 604 else 605 priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL); 606 607 debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode); 608 609 if (mode & SPI_RX_QUAD) 610 debug("quad, tx: "); 611 else if (mode & SPI_RX_DUAL) 612 debug("dual, tx: "); 613 else 614 debug("single, tx: "); 615 616 if (mode & SPI_TX_QUAD) 617 debug("quad\n"); 618 else if (mode & SPI_TX_DUAL) 619 debug("dual\n"); 620 else 621 debug("single\n"); 622 623 return 0; 624 } 625 626 static const struct dm_spi_ops stm32_qspi_ops = { 627 .claim_bus = stm32_qspi_claim_bus, 628 .release_bus = stm32_qspi_release_bus, 629 .xfer = stm32_qspi_xfer, 630 .set_speed = stm32_qspi_set_speed, 631 .set_mode = stm32_qspi_set_mode, 632 }; 633 634 static const struct udevice_id stm32_qspi_ids[] = { 635 { .compatible = "st,stm32-qspi" }, 636 { } 637 }; 638 639 U_BOOT_DRIVER(stm32_qspi) = { 640 .name = "stm32_qspi", 641 .id = UCLASS_SPI, 642 .of_match = stm32_qspi_ids, 643 .ops = &stm32_qspi_ops, 644 .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata, 645 .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata), 646 .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv), 647 .probe = stm32_qspi_probe, 648 .remove = stm32_qspi_remove, 649 }; 650