1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016
4 *
5 * Michael Kurz, <michi.kurz@gmail.com>
6 *
7 * STM32 QSPI driver
8 */
9
10 #include <common.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <malloc.h>
15 #include <reset.h>
16 #include <spi.h>
17 #include <spi_flash.h>
18 #include <asm/io.h>
19 #include <asm/arch/stm32.h>
20 #include <linux/ioport.h>
21
22 struct stm32_qspi_regs {
23 u32 cr; /* 0x00 */
24 u32 dcr; /* 0x04 */
25 u32 sr; /* 0x08 */
26 u32 fcr; /* 0x0C */
27 u32 dlr; /* 0x10 */
28 u32 ccr; /* 0x14 */
29 u32 ar; /* 0x18 */
30 u32 abr; /* 0x1C */
31 u32 dr; /* 0x20 */
32 u32 psmkr; /* 0x24 */
33 u32 psmar; /* 0x28 */
34 u32 pir; /* 0x2C */
35 u32 lptr; /* 0x30 */
36 };
37
38 /*
39 * QUADSPI control register
40 */
41 #define STM32_QSPI_CR_EN BIT(0)
42 #define STM32_QSPI_CR_ABORT BIT(1)
43 #define STM32_QSPI_CR_DMAEN BIT(2)
44 #define STM32_QSPI_CR_TCEN BIT(3)
45 #define STM32_QSPI_CR_SSHIFT BIT(4)
46 #define STM32_QSPI_CR_DFM BIT(6)
47 #define STM32_QSPI_CR_FSEL BIT(7)
48 #define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0)
49 #define STM32_QSPI_CR_FTHRES_SHIFT (8)
50 #define STM32_QSPI_CR_TEIE BIT(16)
51 #define STM32_QSPI_CR_TCIE BIT(17)
52 #define STM32_QSPI_CR_FTIE BIT(18)
53 #define STM32_QSPI_CR_SMIE BIT(19)
54 #define STM32_QSPI_CR_TOIE BIT(20)
55 #define STM32_QSPI_CR_APMS BIT(22)
56 #define STM32_QSPI_CR_PMM BIT(23)
57 #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
58 #define STM32_QSPI_CR_PRESCALER_SHIFT (24)
59
60 /*
61 * QUADSPI device configuration register
62 */
63 #define STM32_QSPI_DCR_CKMODE BIT(0)
64 #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
65 #define STM32_QSPI_DCR_CSHT_SHIFT (8)
66 #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
67 #define STM32_QSPI_DCR_FSIZE_SHIFT (16)
68
69 /*
70 * QUADSPI status register
71 */
72 #define STM32_QSPI_SR_TEF BIT(0)
73 #define STM32_QSPI_SR_TCF BIT(1)
74 #define STM32_QSPI_SR_FTF BIT(2)
75 #define STM32_QSPI_SR_SMF BIT(3)
76 #define STM32_QSPI_SR_TOF BIT(4)
77 #define STM32_QSPI_SR_BUSY BIT(5)
78 #define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0)
79 #define STM32_QSPI_SR_FLEVEL_SHIFT (8)
80
81 /*
82 * QUADSPI flag clear register
83 */
84 #define STM32_QSPI_FCR_CTEF BIT(0)
85 #define STM32_QSPI_FCR_CTCF BIT(1)
86 #define STM32_QSPI_FCR_CSMF BIT(3)
87 #define STM32_QSPI_FCR_CTOF BIT(4)
88
89 /*
90 * QUADSPI communication configuration register
91 */
92 #define STM32_QSPI_CCR_DDRM BIT(31)
93 #define STM32_QSPI_CCR_DHHC BIT(30)
94 #define STM32_QSPI_CCR_SIOO BIT(28)
95 #define STM32_QSPI_CCR_FMODE_SHIFT (26)
96 #define STM32_QSPI_CCR_DMODE_SHIFT (24)
97 #define STM32_QSPI_CCR_DCYC_SHIFT (18)
98 #define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0)
99 #define STM32_QSPI_CCR_ABSIZE_SHIFT (16)
100 #define STM32_QSPI_CCR_ABMODE_SHIFT (14)
101 #define STM32_QSPI_CCR_ADSIZE_SHIFT (12)
102 #define STM32_QSPI_CCR_ADMODE_SHIFT (10)
103 #define STM32_QSPI_CCR_IMODE_SHIFT (8)
104 #define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)
105
106 enum STM32_QSPI_CCR_IMODE {
107 STM32_QSPI_CCR_IMODE_NONE = 0,
108 STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
109 STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
110 STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
111 };
112
113 enum STM32_QSPI_CCR_ADMODE {
114 STM32_QSPI_CCR_ADMODE_NONE = 0,
115 STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
116 STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
117 STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
118 };
119
120 enum STM32_QSPI_CCR_ADSIZE {
121 STM32_QSPI_CCR_ADSIZE_8BIT = 0,
122 STM32_QSPI_CCR_ADSIZE_16BIT = 1,
123 STM32_QSPI_CCR_ADSIZE_24BIT = 2,
124 STM32_QSPI_CCR_ADSIZE_32BIT = 3,
125 };
126
127 enum STM32_QSPI_CCR_ABMODE {
128 STM32_QSPI_CCR_ABMODE_NONE = 0,
129 STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
130 STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
131 STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
132 };
133
134 enum STM32_QSPI_CCR_ABSIZE {
135 STM32_QSPI_CCR_ABSIZE_8BIT = 0,
136 STM32_QSPI_CCR_ABSIZE_16BIT = 1,
137 STM32_QSPI_CCR_ABSIZE_24BIT = 2,
138 STM32_QSPI_CCR_ABSIZE_32BIT = 3,
139 };
140
141 enum STM32_QSPI_CCR_DMODE {
142 STM32_QSPI_CCR_DMODE_NONE = 0,
143 STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
144 STM32_QSPI_CCR_DMODE_TWO_LINE = 2,
145 STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,
146 };
147
148 enum STM32_QSPI_CCR_FMODE {
149 STM32_QSPI_CCR_IND_WRITE = 0,
150 STM32_QSPI_CCR_IND_READ = 1,
151 STM32_QSPI_CCR_AUTO_POLL = 2,
152 STM32_QSPI_CCR_MEM_MAP = 3,
153 };
154
155 /* default SCK frequency, unit: HZ */
156 #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
157
158 #define STM32_MAX_NORCHIP 2
159
160 struct stm32_qspi_platdata {
161 u32 base;
162 u32 memory_map;
163 u32 max_hz;
164 };
165
166 struct stm32_qspi_priv {
167 struct stm32_qspi_regs *regs;
168 ulong clock_rate;
169 u32 max_hz;
170 u32 mode;
171
172 u32 command;
173 u32 address;
174 u32 dummycycles;
175 #define CMD_HAS_ADR BIT(24)
176 #define CMD_HAS_DUMMY BIT(25)
177 #define CMD_HAS_DATA BIT(26)
178 };
179
_stm32_qspi_disable(struct stm32_qspi_priv * priv)180 static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)
181 {
182 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
183 }
184
_stm32_qspi_enable(struct stm32_qspi_priv * priv)185 static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)
186 {
187 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
188 }
189
_stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv * priv)190 static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
191 {
192 while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)
193 ;
194 }
195
_stm32_qspi_wait_for_complete(struct stm32_qspi_priv * priv)196 static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)
197 {
198 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))
199 ;
200 }
201
_stm32_qspi_wait_for_ftf(struct stm32_qspi_priv * priv)202 static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
203 {
204 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))
205 ;
206 }
207
_stm32_qspi_set_flash_size(struct stm32_qspi_priv * priv,u32 size)208 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
209 {
210 u32 fsize = fls(size) - 1;
211
212 clrsetbits_le32(&priv->regs->dcr,
213 STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
214 fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
215 }
216
_stm32_qspi_set_cs(struct stm32_qspi_priv * priv,unsigned int cs)217 static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)
218 {
219 clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
220 cs ? STM32_QSPI_CR_FSEL : 0);
221 }
222
_stm32_qspi_gen_ccr(struct stm32_qspi_priv * priv,u8 fmode)223 static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv, u8 fmode)
224 {
225 unsigned int ccr_reg = 0;
226 u8 imode, admode, dmode;
227 u32 mode = priv->mode;
228 u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
229
230 imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
231 admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
232 dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
233
234 if ((priv->command & CMD_HAS_ADR) && (priv->command & CMD_HAS_DATA)) {
235 if (fmode == STM32_QSPI_CCR_IND_WRITE) {
236 if (mode & SPI_TX_QUAD)
237 dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
238 else if (mode & SPI_TX_DUAL)
239 dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
240 } else if ((fmode == STM32_QSPI_CCR_MEM_MAP) ||
241 (fmode == STM32_QSPI_CCR_IND_READ)) {
242 if (mode & SPI_RX_QUAD)
243 dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
244 else if (mode & SPI_RX_DUAL)
245 dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
246 }
247 }
248
249 if (priv->command & CMD_HAS_DATA)
250 ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);
251
252 if (priv->command & CMD_HAS_DUMMY)
253 ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)
254 << STM32_QSPI_CCR_DCYC_SHIFT);
255
256 if (priv->command & CMD_HAS_ADR) {
257 ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT
258 << STM32_QSPI_CCR_ADSIZE_SHIFT);
259 ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
260 }
261
262 ccr_reg |= (fmode << STM32_QSPI_CCR_FMODE_SHIFT);
263 ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
264 ccr_reg |= cmd;
265
266 return ccr_reg;
267 }
268
_stm32_qspi_enable_mmap(struct stm32_qspi_priv * priv,struct spi_flash * flash)269 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
270 struct spi_flash *flash)
271 {
272 unsigned int ccr_reg;
273
274 priv->command = flash->read_opcode | CMD_HAS_ADR | CMD_HAS_DATA
275 | CMD_HAS_DUMMY;
276 priv->dummycycles = flash->read_dummy;
277
278 ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_MEM_MAP);
279
280 _stm32_qspi_wait_for_not_busy(priv);
281
282 writel(ccr_reg, &priv->regs->ccr);
283
284 priv->dummycycles = 0;
285 }
286
_stm32_qspi_disable_mmap(struct stm32_qspi_priv * priv)287 static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)
288 {
289 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
290 }
291
_stm32_qspi_set_xfer_length(struct stm32_qspi_priv * priv,u32 length)292 static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,
293 u32 length)
294 {
295 writel(length - 1, &priv->regs->dlr);
296 }
297
_stm32_qspi_start_xfer(struct stm32_qspi_priv * priv,u32 cr_reg)298 static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
299 {
300 writel(cr_reg, &priv->regs->ccr);
301
302 if (priv->command & CMD_HAS_ADR)
303 writel(priv->address, &priv->regs->ar);
304 }
305
_stm32_qspi_xfer(struct stm32_qspi_priv * priv,struct spi_flash * flash,unsigned int bitlen,const u8 * dout,u8 * din,unsigned long flags)306 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
307 struct spi_flash *flash, unsigned int bitlen,
308 const u8 *dout, u8 *din, unsigned long flags)
309 {
310 unsigned int words = bitlen / 8;
311 u32 ccr_reg;
312 int i;
313
314 if (flags & SPI_XFER_MMAP) {
315 _stm32_qspi_enable_mmap(priv, flash);
316 return 0;
317 } else if (flags & SPI_XFER_MMAP_END) {
318 _stm32_qspi_disable_mmap(priv);
319 return 0;
320 }
321
322 if (bitlen == 0)
323 return -1;
324
325 if (bitlen % 8) {
326 debug("spi_xfer: Non byte aligned SPI transfer\n");
327 return -1;
328 }
329
330 if (dout && din) {
331 debug("spi_xfer: QSPI cannot have data in and data out set\n");
332 return -1;
333 }
334
335 if (!dout && (flags & SPI_XFER_BEGIN)) {
336 debug("spi_xfer: QSPI transfer must begin with command\n");
337 return -1;
338 }
339
340 if (dout) {
341 if (flags & SPI_XFER_BEGIN) {
342 /* data is command */
343 priv->command = dout[0] | CMD_HAS_DATA;
344 if (words >= 4) {
345 /* address is here too */
346 priv->address = (dout[1] << 16) |
347 (dout[2] << 8) | dout[3];
348 priv->command |= CMD_HAS_ADR;
349 }
350
351 if (words > 4) {
352 /* rest is dummy bytes */
353 priv->dummycycles = (words - 4) * 8;
354 priv->command |= CMD_HAS_DUMMY;
355 }
356
357 if (flags & SPI_XFER_END) {
358 /* command without data */
359 priv->command &= ~(CMD_HAS_DATA);
360 }
361 }
362
363 if (flags & SPI_XFER_END) {
364 ccr_reg = _stm32_qspi_gen_ccr(priv,
365 STM32_QSPI_CCR_IND_WRITE);
366
367 _stm32_qspi_wait_for_not_busy(priv);
368
369 if (priv->command & CMD_HAS_DATA)
370 _stm32_qspi_set_xfer_length(priv, words);
371
372 _stm32_qspi_start_xfer(priv, ccr_reg);
373
374 debug("%s: write: ccr:0x%08x adr:0x%08x\n",
375 __func__, priv->regs->ccr, priv->regs->ar);
376
377 if (priv->command & CMD_HAS_DATA) {
378 _stm32_qspi_wait_for_ftf(priv);
379
380 debug("%s: words:%d data:", __func__, words);
381
382 i = 0;
383 while (words > i) {
384 writeb(dout[i], &priv->regs->dr);
385 debug("%02x ", dout[i]);
386 i++;
387 }
388 debug("\n");
389
390 _stm32_qspi_wait_for_complete(priv);
391 } else {
392 _stm32_qspi_wait_for_not_busy(priv);
393 }
394 }
395 } else if (din) {
396 ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_IND_READ);
397
398 _stm32_qspi_wait_for_not_busy(priv);
399
400 _stm32_qspi_set_xfer_length(priv, words);
401
402 _stm32_qspi_start_xfer(priv, ccr_reg);
403
404 debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,
405 priv->regs->ccr, priv->regs->ar, priv->regs->dlr);
406
407 debug("%s: data:", __func__);
408
409 i = 0;
410 while (words > i) {
411 din[i] = readb(&priv->regs->dr);
412 debug("%02x ", din[i]);
413 i++;
414 }
415 debug("\n");
416 }
417
418 return 0;
419 }
420
stm32_qspi_ofdata_to_platdata(struct udevice * bus)421 static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
422 {
423 struct resource res_regs, res_mem;
424 struct stm32_qspi_platdata *plat = bus->platdata;
425 int ret;
426
427 ret = dev_read_resource_byname(bus, "qspi", &res_regs);
428 if (ret) {
429 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
430 return -ENOMEM;
431 }
432 ret = dev_read_resource_byname(bus, "qspi_mm", &res_mem);
433 if (ret) {
434 debug("Error: can't get mmap base address(ret = %d)!\n", ret);
435 return -ENOMEM;
436 }
437
438 plat->max_hz = dev_read_u32_default(bus, "spi-max-frequency",
439 STM32_QSPI_DEFAULT_SCK_FREQ);
440
441 plat->base = res_regs.start;
442 plat->memory_map = res_mem.start;
443
444 debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",
445 __func__,
446 plat->base,
447 plat->memory_map,
448 plat->max_hz
449 );
450
451 return 0;
452 }
453
stm32_qspi_probe(struct udevice * bus)454 static int stm32_qspi_probe(struct udevice *bus)
455 {
456 struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
457 struct stm32_qspi_priv *priv = dev_get_priv(bus);
458 struct dm_spi_bus *dm_spi_bus;
459 struct clk clk;
460 struct reset_ctl reset_ctl;
461 int ret;
462
463 dm_spi_bus = bus->uclass_priv;
464
465 dm_spi_bus->max_hz = plat->max_hz;
466
467 priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;
468
469 priv->max_hz = plat->max_hz;
470
471 ret = clk_get_by_index(bus, 0, &clk);
472 if (ret < 0)
473 return ret;
474
475 ret = clk_enable(&clk);
476
477 if (ret) {
478 dev_err(bus, "failed to enable clock\n");
479 return ret;
480 }
481
482 priv->clock_rate = clk_get_rate(&clk);
483 if (priv->clock_rate < 0) {
484 clk_disable(&clk);
485 return priv->clock_rate;
486 }
487
488 ret = reset_get_by_index(bus, 0, &reset_ctl);
489 if (ret) {
490 if (ret != -ENOENT) {
491 dev_err(bus, "failed to get reset\n");
492 clk_disable(&clk);
493 return ret;
494 }
495 } else {
496 /* Reset QSPI controller */
497 reset_assert(&reset_ctl);
498 udelay(2);
499 reset_deassert(&reset_ctl);
500 }
501
502 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
503
504 return 0;
505 }
506
stm32_qspi_remove(struct udevice * bus)507 static int stm32_qspi_remove(struct udevice *bus)
508 {
509 return 0;
510 }
511
stm32_qspi_claim_bus(struct udevice * dev)512 static int stm32_qspi_claim_bus(struct udevice *dev)
513 {
514 struct stm32_qspi_priv *priv;
515 struct udevice *bus;
516 struct spi_flash *flash;
517 struct dm_spi_slave_platdata *slave_plat;
518
519 bus = dev->parent;
520 priv = dev_get_priv(bus);
521 flash = dev_get_uclass_priv(dev);
522 slave_plat = dev_get_parent_platdata(dev);
523
524 if (slave_plat->cs >= STM32_MAX_NORCHIP)
525 return -ENODEV;
526
527 _stm32_qspi_set_cs(priv, slave_plat->cs);
528
529 _stm32_qspi_set_flash_size(priv, flash->size);
530
531 _stm32_qspi_enable(priv);
532
533 return 0;
534 }
535
stm32_qspi_release_bus(struct udevice * dev)536 static int stm32_qspi_release_bus(struct udevice *dev)
537 {
538 struct stm32_qspi_priv *priv;
539 struct udevice *bus;
540
541 bus = dev->parent;
542 priv = dev_get_priv(bus);
543
544 _stm32_qspi_disable(priv);
545
546 return 0;
547 }
548
stm32_qspi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)549 static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
550 const void *dout, void *din, unsigned long flags)
551 {
552 struct stm32_qspi_priv *priv;
553 struct udevice *bus;
554 struct spi_flash *flash;
555
556 bus = dev->parent;
557 priv = dev_get_priv(bus);
558 flash = dev_get_uclass_priv(dev);
559
560 return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,
561 (u8 *)din, flags);
562 }
563
stm32_qspi_set_speed(struct udevice * bus,uint speed)564 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
565 {
566 struct stm32_qspi_platdata *plat = bus->platdata;
567 struct stm32_qspi_priv *priv = dev_get_priv(bus);
568 u32 qspi_clk = priv->clock_rate;
569 u32 prescaler = 255;
570 u32 csht;
571
572 if (speed > plat->max_hz)
573 speed = plat->max_hz;
574
575 if (speed > 0) {
576 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
577 if (prescaler > 255)
578 prescaler = 255;
579 else if (prescaler < 0)
580 prescaler = 0;
581 }
582
583 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
584 csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
585
586 _stm32_qspi_wait_for_not_busy(priv);
587
588 clrsetbits_le32(&priv->regs->cr,
589 STM32_QSPI_CR_PRESCALER_MASK <<
590 STM32_QSPI_CR_PRESCALER_SHIFT,
591 prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
592
593 clrsetbits_le32(&priv->regs->dcr,
594 STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
595 csht << STM32_QSPI_DCR_CSHT_SHIFT);
596
597 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
598 (qspi_clk / (prescaler + 1)));
599
600 return 0;
601 }
602
stm32_qspi_set_mode(struct udevice * bus,uint mode)603 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
604 {
605 struct stm32_qspi_priv *priv = dev_get_priv(bus);
606
607 _stm32_qspi_wait_for_not_busy(priv);
608
609 if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
610 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
611 else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
612 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
613 else
614 return -ENODEV;
615
616 if (mode & SPI_CS_HIGH)
617 return -ENODEV;
618
619 if (mode & SPI_RX_QUAD)
620 priv->mode |= SPI_RX_QUAD;
621 else if (mode & SPI_RX_DUAL)
622 priv->mode |= SPI_RX_DUAL;
623 else
624 priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL);
625
626 if (mode & SPI_TX_QUAD)
627 priv->mode |= SPI_TX_QUAD;
628 else if (mode & SPI_TX_DUAL)
629 priv->mode |= SPI_TX_DUAL;
630 else
631 priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL);
632
633 debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
634
635 if (mode & SPI_RX_QUAD)
636 debug("quad, tx: ");
637 else if (mode & SPI_RX_DUAL)
638 debug("dual, tx: ");
639 else
640 debug("single, tx: ");
641
642 if (mode & SPI_TX_QUAD)
643 debug("quad\n");
644 else if (mode & SPI_TX_DUAL)
645 debug("dual\n");
646 else
647 debug("single\n");
648
649 return 0;
650 }
651
652 static const struct dm_spi_ops stm32_qspi_ops = {
653 .claim_bus = stm32_qspi_claim_bus,
654 .release_bus = stm32_qspi_release_bus,
655 .xfer = stm32_qspi_xfer,
656 .set_speed = stm32_qspi_set_speed,
657 .set_mode = stm32_qspi_set_mode,
658 };
659
660 static const struct udevice_id stm32_qspi_ids[] = {
661 { .compatible = "st,stm32-qspi" },
662 { .compatible = "st,stm32f469-qspi" },
663 { }
664 };
665
666 U_BOOT_DRIVER(stm32_qspi) = {
667 .name = "stm32_qspi",
668 .id = UCLASS_SPI,
669 .of_match = stm32_qspi_ids,
670 .ops = &stm32_qspi_ops,
671 .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,
672 .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),
673 .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
674 .probe = stm32_qspi_probe,
675 .remove = stm32_qspi_remove,
676 };
677