xref: /openbmc/u-boot/drivers/spi/sh_spi.c (revision e77e65df)
1 /*
2  * SH SPI driver
3  *
4  * Copyright (C) 2011-2012 Renesas Solutions Corp.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
18  *
19  */
20 
21 #include <common.h>
22 #include <malloc.h>
23 #include <spi.h>
24 #include <asm/io.h>
25 #include "sh_spi.h"
26 
27 static void sh_spi_write(unsigned long data, unsigned long *reg)
28 {
29 	writel(data, reg);
30 }
31 
32 static unsigned long sh_spi_read(unsigned long *reg)
33 {
34 	return readl(reg);
35 }
36 
37 static void sh_spi_set_bit(unsigned long val, unsigned long *reg)
38 {
39 	unsigned long tmp;
40 
41 	tmp = sh_spi_read(reg);
42 	tmp |= val;
43 	sh_spi_write(tmp, reg);
44 }
45 
46 static void sh_spi_clear_bit(unsigned long val, unsigned long *reg)
47 {
48 	unsigned long tmp;
49 
50 	tmp = sh_spi_read(reg);
51 	tmp &= ~val;
52 	sh_spi_write(tmp, reg);
53 }
54 
55 static void clear_fifo(struct sh_spi *ss)
56 {
57 	sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
58 	sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
59 }
60 
61 static int recvbuf_wait(struct sh_spi *ss)
62 {
63 	while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
64 		if (ctrlc())
65 			return 1;
66 		udelay(10);
67 	}
68 	return 0;
69 }
70 
71 static int write_fifo_empty_wait(struct sh_spi *ss)
72 {
73 	while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
74 		if (ctrlc())
75 			return 1;
76 		udelay(10);
77 	}
78 	return 0;
79 }
80 
81 void spi_init(void)
82 {
83 }
84 
85 static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
86 {
87 	unsigned long val = 0;
88 
89 	if (cs & 0x01)
90 		val |= SH_SPI_SSS0;
91 	if (cs & 0x02)
92 		val |= SH_SPI_SSS1;
93 
94 	sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4);
95 	sh_spi_set_bit(val, &ss->regs->cr4);
96 }
97 
98 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
99 		unsigned int max_hz, unsigned int mode)
100 {
101 	struct sh_spi *ss;
102 
103 	if (!spi_cs_is_valid(bus, cs))
104 		return NULL;
105 
106 	ss = spi_alloc_slave(struct sh_spi, bus, cs);
107 	if (!ss)
108 		return NULL;
109 
110 	ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
111 
112 	/* SPI sycle stop */
113 	sh_spi_write(0xfe, &ss->regs->cr1);
114 	/* CR1 init */
115 	sh_spi_write(0x00, &ss->regs->cr1);
116 	/* CR3 init */
117 	sh_spi_write(0x00, &ss->regs->cr3);
118 	sh_spi_set_cs(ss, cs);
119 
120 	clear_fifo(ss);
121 
122 	/* 1/8 clock */
123 	sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2);
124 	udelay(10);
125 
126 	return &ss->slave;
127 }
128 
129 void spi_free_slave(struct spi_slave *slave)
130 {
131 	struct sh_spi *spi = to_sh_spi(slave);
132 
133 	free(spi);
134 }
135 
136 int spi_claim_bus(struct spi_slave *slave)
137 {
138 	return 0;
139 }
140 
141 void spi_release_bus(struct spi_slave *slave)
142 {
143 	struct sh_spi *ss = to_sh_spi(slave);
144 
145 	sh_spi_write(sh_spi_read(&ss->regs->cr1) &
146 		~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1);
147 }
148 
149 static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
150 			unsigned int len, unsigned long flags)
151 {
152 	int i, cur_len, ret = 0;
153 	int remain = (int)len;
154 
155 	if (len >= SH_SPI_FIFO_SIZE)
156 		sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
157 
158 	while (remain > 0) {
159 		cur_len = (remain < SH_SPI_FIFO_SIZE) ?
160 				remain : SH_SPI_FIFO_SIZE;
161 		for (i = 0; i < cur_len &&
162 			!(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) &&
163 			!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF);
164 				i++)
165 			sh_spi_write(tx_data[i], &ss->regs->tbr_rbr);
166 
167 		cur_len = i;
168 
169 		if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) {
170 			/* Abort the transaction */
171 			flags |= SPI_XFER_END;
172 			sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4);
173 			ret = 1;
174 			break;
175 		}
176 
177 		remain -= cur_len;
178 		tx_data += cur_len;
179 
180 		if (remain > 0)
181 			write_fifo_empty_wait(ss);
182 	}
183 
184 	if (flags & SPI_XFER_END) {
185 		sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
186 		sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
187 		udelay(100);
188 		write_fifo_empty_wait(ss);
189 	}
190 
191 	return ret;
192 }
193 
194 static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data,
195 			  unsigned int len, unsigned long flags)
196 {
197 	int i;
198 
199 	if (len > SH_SPI_MAX_BYTE)
200 		sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
201 	else
202 		sh_spi_write(len, &ss->regs->cr3);
203 
204 	sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
205 	sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
206 
207 	for (i = 0; i < len; i++) {
208 		if (recvbuf_wait(ss))
209 			return 0;
210 
211 		rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr);
212 	}
213 	sh_spi_write(0, &ss->regs->cr3);
214 
215 	return 0;
216 }
217 
218 int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
219 		void *din, unsigned long flags)
220 {
221 	struct sh_spi *ss = to_sh_spi(slave);
222 	const unsigned char *tx_data = dout;
223 	unsigned char *rx_data = din;
224 	unsigned int len = bitlen / 8;
225 	int ret = 0;
226 
227 	if (flags & SPI_XFER_BEGIN)
228 		sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA,
229 				&ss->regs->cr1);
230 
231 	if (tx_data)
232 		ret = sh_spi_send(ss, tx_data, len, flags);
233 
234 	if (ret == 0 && rx_data)
235 		ret = sh_spi_receive(ss, rx_data, len, flags);
236 
237 	if (flags & SPI_XFER_END) {
238 		sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1);
239 		udelay(100);
240 
241 		sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD,
242 				 &ss->regs->cr1);
243 		clear_fifo(ss);
244 	}
245 
246 	return ret;
247 }
248 
249 int  spi_cs_is_valid(unsigned int bus, unsigned int cs)
250 {
251 	if (!bus && cs < SH_SPI_NUM_CS)
252 		return 1;
253 	else
254 		return 0;
255 }
256 
257 void spi_cs_activate(struct spi_slave *slave)
258 {
259 
260 }
261 
262 void spi_cs_deactivate(struct spi_slave *slave)
263 {
264 
265 }
266