xref: /openbmc/u-boot/drivers/spi/sh_spi.c (revision c5f18a0b)
1 /*
2  * SH SPI driver
3  *
4  * Copyright (C) 2011-2012 Renesas Solutions Corp.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
18  *
19  */
20 
21 #include <common.h>
22 #include <console.h>
23 #include <malloc.h>
24 #include <spi.h>
25 #include <asm/io.h>
26 #include "sh_spi.h"
27 
28 static void sh_spi_write(unsigned long data, unsigned long *reg)
29 {
30 	writel(data, reg);
31 }
32 
33 static unsigned long sh_spi_read(unsigned long *reg)
34 {
35 	return readl(reg);
36 }
37 
38 static void sh_spi_set_bit(unsigned long val, unsigned long *reg)
39 {
40 	unsigned long tmp;
41 
42 	tmp = sh_spi_read(reg);
43 	tmp |= val;
44 	sh_spi_write(tmp, reg);
45 }
46 
47 static void sh_spi_clear_bit(unsigned long val, unsigned long *reg)
48 {
49 	unsigned long tmp;
50 
51 	tmp = sh_spi_read(reg);
52 	tmp &= ~val;
53 	sh_spi_write(tmp, reg);
54 }
55 
56 static void clear_fifo(struct sh_spi *ss)
57 {
58 	sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
59 	sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
60 }
61 
62 static int recvbuf_wait(struct sh_spi *ss)
63 {
64 	while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
65 		if (ctrlc())
66 			return 1;
67 		udelay(10);
68 	}
69 	return 0;
70 }
71 
72 static int write_fifo_empty_wait(struct sh_spi *ss)
73 {
74 	while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
75 		if (ctrlc())
76 			return 1;
77 		udelay(10);
78 	}
79 	return 0;
80 }
81 
82 void spi_init(void)
83 {
84 }
85 
86 static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
87 {
88 	unsigned long val = 0;
89 
90 	if (cs & 0x01)
91 		val |= SH_SPI_SSS0;
92 	if (cs & 0x02)
93 		val |= SH_SPI_SSS1;
94 
95 	sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4);
96 	sh_spi_set_bit(val, &ss->regs->cr4);
97 }
98 
99 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
100 		unsigned int max_hz, unsigned int mode)
101 {
102 	struct sh_spi *ss;
103 
104 	if (!spi_cs_is_valid(bus, cs))
105 		return NULL;
106 
107 	ss = spi_alloc_slave(struct sh_spi, bus, cs);
108 	if (!ss)
109 		return NULL;
110 
111 	ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
112 
113 	/* SPI sycle stop */
114 	sh_spi_write(0xfe, &ss->regs->cr1);
115 	/* CR1 init */
116 	sh_spi_write(0x00, &ss->regs->cr1);
117 	/* CR3 init */
118 	sh_spi_write(0x00, &ss->regs->cr3);
119 	sh_spi_set_cs(ss, cs);
120 
121 	clear_fifo(ss);
122 
123 	/* 1/8 clock */
124 	sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2);
125 	udelay(10);
126 
127 	return &ss->slave;
128 }
129 
130 void spi_free_slave(struct spi_slave *slave)
131 {
132 	struct sh_spi *spi = to_sh_spi(slave);
133 
134 	free(spi);
135 }
136 
137 int spi_claim_bus(struct spi_slave *slave)
138 {
139 	return 0;
140 }
141 
142 void spi_release_bus(struct spi_slave *slave)
143 {
144 	struct sh_spi *ss = to_sh_spi(slave);
145 
146 	sh_spi_write(sh_spi_read(&ss->regs->cr1) &
147 		~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1);
148 }
149 
150 static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
151 			unsigned int len, unsigned long flags)
152 {
153 	int i, cur_len, ret = 0;
154 	int remain = (int)len;
155 
156 	if (len >= SH_SPI_FIFO_SIZE)
157 		sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
158 
159 	while (remain > 0) {
160 		cur_len = (remain < SH_SPI_FIFO_SIZE) ?
161 				remain : SH_SPI_FIFO_SIZE;
162 		for (i = 0; i < cur_len &&
163 			!(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) &&
164 			!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF);
165 				i++)
166 			sh_spi_write(tx_data[i], &ss->regs->tbr_rbr);
167 
168 		cur_len = i;
169 
170 		if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) {
171 			/* Abort the transaction */
172 			flags |= SPI_XFER_END;
173 			sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4);
174 			ret = 1;
175 			break;
176 		}
177 
178 		remain -= cur_len;
179 		tx_data += cur_len;
180 
181 		if (remain > 0)
182 			write_fifo_empty_wait(ss);
183 	}
184 
185 	if (flags & SPI_XFER_END) {
186 		sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
187 		sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
188 		udelay(100);
189 		write_fifo_empty_wait(ss);
190 	}
191 
192 	return ret;
193 }
194 
195 static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data,
196 			  unsigned int len, unsigned long flags)
197 {
198 	int i;
199 
200 	if (len > SH_SPI_MAX_BYTE)
201 		sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
202 	else
203 		sh_spi_write(len, &ss->regs->cr3);
204 
205 	sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
206 	sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
207 
208 	for (i = 0; i < len; i++) {
209 		if (recvbuf_wait(ss))
210 			return 0;
211 
212 		rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr);
213 	}
214 	sh_spi_write(0, &ss->regs->cr3);
215 
216 	return 0;
217 }
218 
219 int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
220 		void *din, unsigned long flags)
221 {
222 	struct sh_spi *ss = to_sh_spi(slave);
223 	const unsigned char *tx_data = dout;
224 	unsigned char *rx_data = din;
225 	unsigned int len = bitlen / 8;
226 	int ret = 0;
227 
228 	if (flags & SPI_XFER_BEGIN)
229 		sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA,
230 				&ss->regs->cr1);
231 
232 	if (tx_data)
233 		ret = sh_spi_send(ss, tx_data, len, flags);
234 
235 	if (ret == 0 && rx_data)
236 		ret = sh_spi_receive(ss, rx_data, len, flags);
237 
238 	if (flags & SPI_XFER_END) {
239 		sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1);
240 		udelay(100);
241 
242 		sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD,
243 				 &ss->regs->cr1);
244 		clear_fifo(ss);
245 	}
246 
247 	return ret;
248 }
249 
250 int  spi_cs_is_valid(unsigned int bus, unsigned int cs)
251 {
252 	if (!bus && cs < SH_SPI_NUM_CS)
253 		return 1;
254 	else
255 		return 0;
256 }
257 
258 void spi_cs_activate(struct spi_slave *slave)
259 {
260 
261 }
262 
263 void spi_cs_deactivate(struct spi_slave *slave)
264 {
265 
266 }
267