1 /* 2 * SH QSPI (Quad SPI) driver 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <console.h> 12 #include <malloc.h> 13 #include <spi.h> 14 #include <wait_bit.h> 15 #include <asm/arch/rmobile.h> 16 #include <asm/io.h> 17 18 /* SH QSPI register bit masks <REG>_<BIT> */ 19 #define SPCR_MSTR 0x08 20 #define SPCR_SPE 0x40 21 #define SPSR_SPRFF 0x80 22 #define SPSR_SPTEF 0x20 23 #define SPPCR_IO3FV 0x04 24 #define SPPCR_IO2FV 0x02 25 #define SPPCR_IO1FV 0x01 26 #define SPBDCR_RXBC0 BIT(0) 27 #define SPCMD_SCKDEN BIT(15) 28 #define SPCMD_SLNDEN BIT(14) 29 #define SPCMD_SPNDEN BIT(13) 30 #define SPCMD_SSLKP BIT(7) 31 #define SPCMD_BRDV0 BIT(2) 32 #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \ 33 SPCMD_SPNDEN | SPCMD_SSLKP | \ 34 SPCMD_BRDV0 35 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \ 36 SPCMD_BRDV0 37 #define SPBFCR_TXRST BIT(7) 38 #define SPBFCR_RXRST BIT(6) 39 #define SPBFCR_TXTRG 0x30 40 #define SPBFCR_RXTRG 0x07 41 42 /* SH QSPI register set */ 43 struct sh_qspi_regs { 44 u8 spcr; 45 u8 sslp; 46 u8 sppcr; 47 u8 spsr; 48 u32 spdr; 49 u8 spscr; 50 u8 spssr; 51 u8 spbr; 52 u8 spdcr; 53 u8 spckd; 54 u8 sslnd; 55 u8 spnd; 56 u8 dummy0; 57 u16 spcmd0; 58 u16 spcmd1; 59 u16 spcmd2; 60 u16 spcmd3; 61 u8 spbfcr; 62 u8 dummy1; 63 u16 spbdcr; 64 u32 spbmul0; 65 u32 spbmul1; 66 u32 spbmul2; 67 u32 spbmul3; 68 }; 69 70 struct sh_qspi_slave { 71 struct spi_slave slave; 72 struct sh_qspi_regs *regs; 73 }; 74 75 static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave) 76 { 77 return container_of(slave, struct sh_qspi_slave, slave); 78 } 79 80 static void sh_qspi_init(struct sh_qspi_slave *ss) 81 { 82 /* QSPI initialize */ 83 /* Set master mode only */ 84 writeb(SPCR_MSTR, &ss->regs->spcr); 85 86 /* Set SSL signal level */ 87 writeb(0x00, &ss->regs->sslp); 88 89 /* Set MOSI signal value when transfer is in idle state */ 90 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr); 91 92 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */ 93 writeb(0x01, &ss->regs->spbr); 94 95 /* Disable Dummy Data Transmission */ 96 writeb(0x00, &ss->regs->spdcr); 97 98 /* Set clock delay value */ 99 writeb(0x00, &ss->regs->spckd); 100 101 /* Set SSL negation delay value */ 102 writeb(0x00, &ss->regs->sslnd); 103 104 /* Set next-access delay value */ 105 writeb(0x00, &ss->regs->spnd); 106 107 /* Set equence command */ 108 writew(SPCMD_INIT2, &ss->regs->spcmd0); 109 110 /* Reset transfer and receive Buffer */ 111 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); 112 113 /* Clear transfer and receive Buffer control bit */ 114 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); 115 116 /* Set equence control method. Use equence0 only */ 117 writeb(0x00, &ss->regs->spscr); 118 119 /* Enable SPI function */ 120 setbits_8(&ss->regs->spcr, SPCR_SPE); 121 } 122 123 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 124 { 125 return 1; 126 } 127 128 void spi_cs_activate(struct spi_slave *slave) 129 { 130 struct sh_qspi_slave *ss = to_sh_qspi(slave); 131 132 /* Set master mode only */ 133 writeb(SPCR_MSTR, &ss->regs->spcr); 134 135 /* Set command */ 136 writew(SPCMD_INIT1, &ss->regs->spcmd0); 137 138 /* Reset transfer and receive Buffer */ 139 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); 140 141 /* Clear transfer and receive Buffer control bit */ 142 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); 143 144 /* Set equence control method. Use equence0 only */ 145 writeb(0x00, &ss->regs->spscr); 146 147 /* Enable SPI function */ 148 setbits_8(&ss->regs->spcr, SPCR_SPE); 149 } 150 151 void spi_cs_deactivate(struct spi_slave *slave) 152 { 153 struct sh_qspi_slave *ss = to_sh_qspi(slave); 154 155 /* Disable SPI Function */ 156 clrbits_8(&ss->regs->spcr, SPCR_SPE); 157 } 158 159 void spi_init(void) 160 { 161 /* nothing to do */ 162 } 163 164 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 165 unsigned int max_hz, unsigned int mode) 166 { 167 struct sh_qspi_slave *ss; 168 169 if (!spi_cs_is_valid(bus, cs)) 170 return NULL; 171 172 ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs); 173 if (!ss) { 174 printf("SPI_error: Fail to allocate sh_qspi_slave\n"); 175 return NULL; 176 } 177 178 ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE; 179 180 /* Init SH QSPI */ 181 sh_qspi_init(ss); 182 183 return &ss->slave; 184 } 185 186 void spi_free_slave(struct spi_slave *slave) 187 { 188 struct sh_qspi_slave *spi = to_sh_qspi(slave); 189 190 free(spi); 191 } 192 193 int spi_claim_bus(struct spi_slave *slave) 194 { 195 return 0; 196 } 197 198 void spi_release_bus(struct spi_slave *slave) 199 { 200 } 201 202 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 203 void *din, unsigned long flags) 204 { 205 struct sh_qspi_slave *ss = to_sh_qspi(slave); 206 u32 nbyte, chunk; 207 int i, ret = 0; 208 u8 dtdata = 0, drdata; 209 u8 *tdata = &dtdata, *rdata = &drdata; 210 u32 *spbmul0 = &ss->regs->spbmul0; 211 212 if (dout == NULL && din == NULL) { 213 if (flags & SPI_XFER_END) 214 spi_cs_deactivate(slave); 215 return 0; 216 } 217 218 if (bitlen % 8) { 219 printf("%s: bitlen is not 8bit alined %d", __func__, bitlen); 220 return 1; 221 } 222 223 nbyte = bitlen / 8; 224 225 if (flags & SPI_XFER_BEGIN) { 226 spi_cs_activate(slave); 227 228 /* Set 1048576 byte */ 229 writel(0x100000, spbmul0); 230 } 231 232 if (flags & SPI_XFER_END) 233 writel(nbyte, spbmul0); 234 235 if (dout != NULL) 236 tdata = (u8 *)dout; 237 238 if (din != NULL) 239 rdata = din; 240 241 while (nbyte > 0) { 242 /* 243 * Check if there is 32 Byte chunk and if there is, transfer 244 * it in one burst, otherwise transfer on byte-by-byte basis. 245 */ 246 chunk = (nbyte >= 32) ? 32 : 1; 247 248 clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG, 249 chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0); 250 251 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF, 252 true, 1000, true); 253 if (ret) 254 return ret; 255 256 for (i = 0; i < chunk; i++) { 257 writeb(*tdata, &ss->regs->spdr); 258 if (dout != NULL) 259 tdata++; 260 } 261 262 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF, 263 true, 1000, true); 264 if (ret) 265 return ret; 266 267 for (i = 0; i < chunk; i++) { 268 *rdata = readb(&ss->regs->spdr); 269 if (din != NULL) 270 rdata++; 271 } 272 273 nbyte -= chunk; 274 } 275 276 if (flags & SPI_XFER_END) 277 spi_cs_deactivate(slave); 278 279 return ret; 280 } 281