1 /* 2 * spi driver for rockchip 3 * 4 * (C) Copyright 2015 Google, Inc 5 * 6 * (C) Copyright 2008-2013 Rockchip Electronics 7 * Peter, Software Engineering, <superpeter.cai@gmail.com>. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <errno.h> 16 #include <spi.h> 17 #include <asm/errno.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/periph.h> 21 #include <dm/pinctrl.h> 22 #include "rk_spi.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* Change to 1 to output registers at the start of each transaction */ 27 #define DEBUG_RK_SPI 0 28 29 struct rockchip_spi_platdata { 30 enum periph_id periph_id; 31 struct udevice *pinctrl; 32 s32 frequency; /* Default clock frequency, -1 for none */ 33 fdt_addr_t base; 34 uint deactivate_delay_us; /* Delay to wait after deactivate */ 35 }; 36 37 struct rockchip_spi_priv { 38 struct rockchip_spi *regs; 39 struct udevice *clk_gpll; 40 unsigned int max_freq; 41 unsigned int mode; 42 enum periph_id periph_id; /* Peripheral ID for this device */ 43 ulong last_transaction_us; /* Time of last transaction end */ 44 u8 bits_per_word; /* max 16 bits per word */ 45 u8 n_bytes; 46 unsigned int speed_hz; 47 unsigned int tmode; 48 uint input_rate; 49 }; 50 51 #define SPI_FIFO_DEPTH 32 52 53 static void rkspi_dump_regs(struct rockchip_spi *regs) 54 { 55 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0)); 56 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1)); 57 debug("ssienr: \t\t0x%08x\n", readl(®s->enr)); 58 debug("ser: \t\t0x%08x\n", readl(®s->ser)); 59 debug("baudr: \t\t0x%08x\n", readl(®s->baudr)); 60 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr)); 61 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr)); 62 debug("txflr: \t\t0x%08x\n", readl(®s->txflr)); 63 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr)); 64 debug("sr: \t\t0x%08x\n", readl(®s->sr)); 65 debug("imr: \t\t0x%08x\n", readl(®s->imr)); 66 debug("isr: \t\t0x%08x\n", readl(®s->isr)); 67 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr)); 68 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr)); 69 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr)); 70 } 71 72 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable) 73 { 74 writel(enable ? 1 : 0, ®s->enr); 75 } 76 77 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed) 78 { 79 uint clk_div; 80 81 clk_div = clk_get_divisor(priv->input_rate, speed); 82 debug("spi speed %u, div %u\n", speed, clk_div); 83 84 writel(clk_div, &priv->regs->baudr); 85 } 86 87 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs) 88 { 89 unsigned long start; 90 91 start = get_timer(0); 92 while (readl(®s->sr) & SR_BUSY) { 93 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) { 94 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n"); 95 return -ETIMEDOUT; 96 } 97 } 98 99 return 0; 100 } 101 102 static void spi_cs_activate(struct rockchip_spi *regs, uint cs) 103 { 104 debug("activate cs%u\n", cs); 105 writel(1 << cs, ®s->ser); 106 } 107 108 static void spi_cs_deactivate(struct rockchip_spi *regs, uint cs) 109 { 110 debug("deactivate cs%u\n", cs); 111 writel(0, ®s->ser); 112 } 113 114 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) 115 { 116 struct rockchip_spi_platdata *plat = bus->platdata; 117 const void *blob = gd->fdt_blob; 118 int node = bus->of_offset; 119 int ret; 120 121 plat->base = dev_get_addr(bus); 122 ret = uclass_get_device(UCLASS_PINCTRL, 0, &plat->pinctrl); 123 if (ret) 124 return ret; 125 ret = pinctrl_get_periph_id(plat->pinctrl, bus); 126 127 if (ret < 0) { 128 debug("%s: Could not get peripheral ID for %s: %d\n", __func__, 129 bus->name, ret); 130 return -FDT_ERR_NOTFOUND; 131 } 132 plat->periph_id = ret; 133 134 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 135 50000000); 136 plat->deactivate_delay_us = fdtdec_get_int(blob, node, 137 "spi-deactivate-delay", 0); 138 debug("%s: base=%x, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", 139 __func__, plat->base, plat->periph_id, plat->frequency, 140 plat->deactivate_delay_us); 141 142 return 0; 143 } 144 145 static int rockchip_spi_probe(struct udevice *bus) 146 { 147 struct rockchip_spi_platdata *plat = dev_get_platdata(bus); 148 struct rockchip_spi_priv *priv = dev_get_priv(bus); 149 int ret; 150 151 debug("%s: probe\n", __func__); 152 priv->regs = (struct rockchip_spi *)plat->base; 153 154 priv->last_transaction_us = timer_get_us(); 155 priv->max_freq = plat->frequency; 156 priv->periph_id = plat->periph_id; 157 ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &priv->clk_gpll); 158 if (ret) { 159 debug("%s: Failed to find CLK_GENERAL: %d\n", __func__, ret); 160 return ret; 161 } 162 163 /* 164 * Use 99 MHz as our clock since it divides nicely into 594 MHz which 165 * is the assumed speed for CLK_GENERAL. 166 */ 167 ret = clk_set_periph_rate(priv->clk_gpll, plat->periph_id, 99000000); 168 if (ret < 0) { 169 debug("%s: Failed to set clock: %d\n", __func__, ret); 170 return ret; 171 } 172 priv->input_rate = ret; 173 debug("%s: rate = %u\n", __func__, priv->input_rate); 174 priv->bits_per_word = 8; 175 priv->tmode = TMOD_TR; /* Tx & Rx */ 176 177 return 0; 178 } 179 180 static int rockchip_spi_claim_bus(struct udevice *dev) 181 { 182 struct udevice *bus = dev->parent; 183 struct rockchip_spi_platdata *plat = dev_get_platdata(bus); 184 struct rockchip_spi_priv *priv = dev_get_priv(bus); 185 struct rockchip_spi *regs = priv->regs; 186 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 187 u8 spi_dfs, spi_tf; 188 uint ctrlr0; 189 int ret; 190 191 /* Disable the SPI hardware */ 192 rkspi_enable_chip(regs, 0); 193 194 switch (priv->bits_per_word) { 195 case 8: 196 priv->n_bytes = 1; 197 spi_dfs = DFS_8BIT; 198 spi_tf = HALF_WORD_OFF; 199 break; 200 case 16: 201 priv->n_bytes = 2; 202 spi_dfs = DFS_16BIT; 203 spi_tf = HALF_WORD_ON; 204 break; 205 default: 206 debug("%s: unsupported bits: %dbits\n", __func__, 207 priv->bits_per_word); 208 return -EPROTONOSUPPORT; 209 } 210 211 rkspi_set_clk(priv, priv->speed_hz); 212 213 /* Operation Mode */ 214 ctrlr0 = OMOD_MASTER << OMOD_SHIFT; 215 216 /* Data Frame Size */ 217 ctrlr0 |= spi_dfs & DFS_MASK << DFS_SHIFT; 218 219 /* set SPI mode 0..3 */ 220 if (priv->mode & SPI_CPOL) 221 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT; 222 if (priv->mode & SPI_CPHA) 223 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT; 224 225 /* Chip Select Mode */ 226 ctrlr0 |= CSM_KEEP << CSM_SHIFT; 227 228 /* SSN to Sclk_out delay */ 229 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT; 230 231 /* Serial Endian Mode */ 232 ctrlr0 |= SEM_LITTLE << SEM_SHIFT; 233 234 /* First Bit Mode */ 235 ctrlr0 |= FBM_MSB << FBM_SHIFT; 236 237 /* Byte and Halfword Transform */ 238 ctrlr0 |= (spi_tf & HALF_WORD_MASK) << HALF_WORD_TX_SHIFT; 239 240 /* Rxd Sample Delay */ 241 ctrlr0 |= 0 << RXDSD_SHIFT; 242 243 /* Frame Format */ 244 ctrlr0 |= FRF_SPI << FRF_SHIFT; 245 246 /* Tx and Rx mode */ 247 ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT; 248 249 writel(ctrlr0, ®s->ctrlr0); 250 251 ret = pinctrl_request(plat->pinctrl, priv->periph_id, slave_plat->cs); 252 if (ret) { 253 debug("%s: Cannot request pinctrl: %d\n", __func__, ret); 254 return ret; 255 } 256 257 return 0; 258 } 259 260 static int rockchip_spi_release_bus(struct udevice *dev) 261 { 262 return 0; 263 } 264 265 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, 266 const void *dout, void *din, unsigned long flags) 267 { 268 struct udevice *bus = dev->parent; 269 struct rockchip_spi_priv *priv = dev_get_priv(bus); 270 struct rockchip_spi *regs = priv->regs; 271 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 272 int len = bitlen >> 3; 273 const u8 *out = dout; 274 u8 *in = din; 275 int toread, towrite; 276 int ret; 277 278 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, 279 len, flags); 280 if (DEBUG_RK_SPI) 281 rkspi_dump_regs(regs); 282 283 /* Assert CS before transfer */ 284 if (flags & SPI_XFER_BEGIN) 285 spi_cs_activate(regs, slave_plat->cs); 286 287 while (len > 0) { 288 int todo = min(len, 0xffff); 289 290 rkspi_enable_chip(regs, true); 291 writel(todo - 1, ®s->ctrlr1); 292 rkspi_enable_chip(regs, true); 293 294 toread = todo; 295 towrite = todo; 296 while (toread || towrite) { 297 u32 status = readl(®s->sr); 298 299 if (towrite && !(status & SR_TF_FULL)) { 300 writel(out ? *out++ : 0, regs->txdr); 301 towrite--; 302 } 303 if (toread && !(status & SR_RF_EMPT)) { 304 u32 byte = readl(regs->rxdr); 305 306 if (in) 307 *in++ = byte; 308 toread--; 309 } 310 } 311 ret = rkspi_wait_till_not_busy(regs); 312 if (ret) 313 break; 314 len -= todo; 315 } 316 317 /* Deassert CS after transfer */ 318 if (flags & SPI_XFER_END) 319 spi_cs_deactivate(regs, slave_plat->cs); 320 321 rkspi_enable_chip(regs, false); 322 323 return ret; 324 } 325 326 static int rockchip_spi_set_speed(struct udevice *bus, uint speed) 327 { 328 struct rockchip_spi_priv *priv = dev_get_priv(bus); 329 330 if (speed > ROCKCHIP_SPI_MAX_RATE) 331 return -EINVAL; 332 if (speed > priv->max_freq) 333 speed = priv->max_freq; 334 priv->speed_hz = speed; 335 336 return 0; 337 } 338 339 static int rockchip_spi_set_mode(struct udevice *bus, uint mode) 340 { 341 struct rockchip_spi_priv *priv = dev_get_priv(bus); 342 343 priv->mode = mode; 344 345 return 0; 346 } 347 348 static const struct dm_spi_ops rockchip_spi_ops = { 349 .claim_bus = rockchip_spi_claim_bus, 350 .release_bus = rockchip_spi_release_bus, 351 .xfer = rockchip_spi_xfer, 352 .set_speed = rockchip_spi_set_speed, 353 .set_mode = rockchip_spi_set_mode, 354 /* 355 * cs_info is not needed, since we require all chip selects to be 356 * in the device tree explicitly 357 */ 358 }; 359 360 static const struct udevice_id rockchip_spi_ids[] = { 361 { .compatible = "rockchip,rk3288-spi" }, 362 { } 363 }; 364 365 U_BOOT_DRIVER(rockchip_spi) = { 366 .name = "rockchip_spi", 367 .id = UCLASS_SPI, 368 .of_match = rockchip_spi_ids, 369 .ops = &rockchip_spi_ops, 370 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata, 371 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata), 372 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv), 373 .probe = rockchip_spi_probe, 374 }; 375