1 /* 2 * spi driver for rockchip 3 * 4 * (C) Copyright 2015 Google, Inc 5 * 6 * (C) Copyright 2008-2013 Rockchip Electronics 7 * Peter, Software Engineering, <superpeter.cai@gmail.com>. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <dt-structs.h> 16 #include <errno.h> 17 #include <spi.h> 18 #include <linux/errno.h> 19 #include <asm/io.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/periph.h> 22 #include <dm/pinctrl.h> 23 #include "rk_spi.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 /* Change to 1 to output registers at the start of each transaction */ 28 #define DEBUG_RK_SPI 0 29 30 struct rockchip_spi_platdata { 31 #if CONFIG_IS_ENABLED(OF_PLATDATA) 32 struct dtd_rockchip_rk3288_spi of_plat; 33 #endif 34 s32 frequency; /* Default clock frequency, -1 for none */ 35 fdt_addr_t base; 36 uint deactivate_delay_us; /* Delay to wait after deactivate */ 37 uint activate_delay_us; /* Delay to wait after activate */ 38 }; 39 40 struct rockchip_spi_priv { 41 struct rockchip_spi *regs; 42 struct clk clk; 43 unsigned int max_freq; 44 unsigned int mode; 45 ulong last_transaction_us; /* Time of last transaction end */ 46 u8 bits_per_word; /* max 16 bits per word */ 47 u8 n_bytes; 48 unsigned int speed_hz; 49 unsigned int last_speed_hz; 50 unsigned int tmode; 51 uint input_rate; 52 }; 53 54 #define SPI_FIFO_DEPTH 32 55 56 static void rkspi_dump_regs(struct rockchip_spi *regs) 57 { 58 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0)); 59 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1)); 60 debug("ssienr: \t\t0x%08x\n", readl(®s->enr)); 61 debug("ser: \t\t0x%08x\n", readl(®s->ser)); 62 debug("baudr: \t\t0x%08x\n", readl(®s->baudr)); 63 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr)); 64 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr)); 65 debug("txflr: \t\t0x%08x\n", readl(®s->txflr)); 66 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr)); 67 debug("sr: \t\t0x%08x\n", readl(®s->sr)); 68 debug("imr: \t\t0x%08x\n", readl(®s->imr)); 69 debug("isr: \t\t0x%08x\n", readl(®s->isr)); 70 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr)); 71 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr)); 72 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr)); 73 } 74 75 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable) 76 { 77 writel(enable ? 1 : 0, ®s->enr); 78 } 79 80 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed) 81 { 82 uint clk_div; 83 84 clk_div = clk_get_divisor(priv->input_rate, speed); 85 debug("spi speed %u, div %u\n", speed, clk_div); 86 87 writel(clk_div, &priv->regs->baudr); 88 priv->last_speed_hz = speed; 89 } 90 91 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs) 92 { 93 unsigned long start; 94 95 start = get_timer(0); 96 while (readl(®s->sr) & SR_BUSY) { 97 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) { 98 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n"); 99 return -ETIMEDOUT; 100 } 101 } 102 103 return 0; 104 } 105 106 static void spi_cs_activate(struct udevice *dev, uint cs) 107 { 108 struct udevice *bus = dev->parent; 109 struct rockchip_spi_platdata *plat = bus->platdata; 110 struct rockchip_spi_priv *priv = dev_get_priv(bus); 111 struct rockchip_spi *regs = priv->regs; 112 113 /* If it's too soon to do another transaction, wait */ 114 if (plat->deactivate_delay_us && priv->last_transaction_us) { 115 ulong delay_us; /* The delay completed so far */ 116 delay_us = timer_get_us() - priv->last_transaction_us; 117 if (delay_us < plat->deactivate_delay_us) 118 udelay(plat->deactivate_delay_us - delay_us); 119 } 120 121 debug("activate cs%u\n", cs); 122 writel(1 << cs, ®s->ser); 123 if (plat->activate_delay_us) 124 udelay(plat->activate_delay_us); 125 } 126 127 static void spi_cs_deactivate(struct udevice *dev, uint cs) 128 { 129 struct udevice *bus = dev->parent; 130 struct rockchip_spi_platdata *plat = bus->platdata; 131 struct rockchip_spi_priv *priv = dev_get_priv(bus); 132 struct rockchip_spi *regs = priv->regs; 133 134 debug("deactivate cs%u\n", cs); 135 writel(0, ®s->ser); 136 137 /* Remember time of this transaction so we can honour the bus delay */ 138 if (plat->deactivate_delay_us) 139 priv->last_transaction_us = timer_get_us(); 140 } 141 142 #if CONFIG_IS_ENABLED(OF_PLATDATA) 143 static int conv_of_platdata(struct udevice *dev) 144 { 145 struct rockchip_spi_platdata *plat = dev->platdata; 146 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat; 147 struct rockchip_spi_priv *priv = dev_get_priv(dev); 148 int ret; 149 150 plat->base = dtplat->reg[0]; 151 plat->frequency = 20000000; 152 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); 153 if (ret < 0) 154 return ret; 155 dev->req_seq = 0; 156 157 return 0; 158 } 159 #endif 160 161 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) 162 { 163 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 164 struct rockchip_spi_platdata *plat = dev_get_platdata(bus); 165 struct rockchip_spi_priv *priv = dev_get_priv(bus); 166 const void *blob = gd->fdt_blob; 167 int node = bus->of_offset; 168 int ret; 169 170 plat->base = dev_get_addr(bus); 171 172 ret = clk_get_by_index(bus, 0, &priv->clk); 173 if (ret < 0) { 174 debug("%s: Could not get clock for %s: %d\n", __func__, 175 bus->name, ret); 176 return ret; 177 } 178 179 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 180 50000000); 181 plat->deactivate_delay_us = fdtdec_get_int(blob, node, 182 "spi-deactivate-delay", 0); 183 plat->activate_delay_us = fdtdec_get_int(blob, node, 184 "spi-activate-delay", 0); 185 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", 186 __func__, (uint)plat->base, plat->frequency, 187 plat->deactivate_delay_us); 188 #endif 189 190 return 0; 191 } 192 193 static int rockchip_spi_probe(struct udevice *bus) 194 { 195 struct rockchip_spi_platdata *plat = dev_get_platdata(bus); 196 struct rockchip_spi_priv *priv = dev_get_priv(bus); 197 int ret; 198 199 debug("%s: probe\n", __func__); 200 #if CONFIG_IS_ENABLED(OF_PLATDATA) 201 ret = conv_of_platdata(bus); 202 if (ret) 203 return ret; 204 #endif 205 priv->regs = (struct rockchip_spi *)plat->base; 206 207 priv->last_transaction_us = timer_get_us(); 208 priv->max_freq = plat->frequency; 209 210 /* 211 * Use 99 MHz as our clock since it divides nicely into 594 MHz which 212 * is the assumed speed for CLK_GENERAL. 213 */ 214 ret = clk_set_rate(&priv->clk, 99000000); 215 if (ret < 0) { 216 debug("%s: Failed to set clock: %d\n", __func__, ret); 217 return ret; 218 } 219 priv->input_rate = ret; 220 debug("%s: rate = %u\n", __func__, priv->input_rate); 221 priv->bits_per_word = 8; 222 priv->tmode = TMOD_TR; /* Tx & Rx */ 223 224 return 0; 225 } 226 227 static int rockchip_spi_claim_bus(struct udevice *dev) 228 { 229 struct udevice *bus = dev->parent; 230 struct rockchip_spi_priv *priv = dev_get_priv(bus); 231 struct rockchip_spi *regs = priv->regs; 232 u8 spi_dfs, spi_tf; 233 uint ctrlr0; 234 235 /* Disable the SPI hardware */ 236 rkspi_enable_chip(regs, 0); 237 238 switch (priv->bits_per_word) { 239 case 8: 240 priv->n_bytes = 1; 241 spi_dfs = DFS_8BIT; 242 spi_tf = HALF_WORD_OFF; 243 break; 244 case 16: 245 priv->n_bytes = 2; 246 spi_dfs = DFS_16BIT; 247 spi_tf = HALF_WORD_ON; 248 break; 249 default: 250 debug("%s: unsupported bits: %dbits\n", __func__, 251 priv->bits_per_word); 252 return -EPROTONOSUPPORT; 253 } 254 255 if (priv->speed_hz != priv->last_speed_hz) 256 rkspi_set_clk(priv, priv->speed_hz); 257 258 /* Operation Mode */ 259 ctrlr0 = OMOD_MASTER << OMOD_SHIFT; 260 261 /* Data Frame Size */ 262 ctrlr0 |= spi_dfs << DFS_SHIFT; 263 264 /* set SPI mode 0..3 */ 265 if (priv->mode & SPI_CPOL) 266 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT; 267 if (priv->mode & SPI_CPHA) 268 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT; 269 270 /* Chip Select Mode */ 271 ctrlr0 |= CSM_KEEP << CSM_SHIFT; 272 273 /* SSN to Sclk_out delay */ 274 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT; 275 276 /* Serial Endian Mode */ 277 ctrlr0 |= SEM_LITTLE << SEM_SHIFT; 278 279 /* First Bit Mode */ 280 ctrlr0 |= FBM_MSB << FBM_SHIFT; 281 282 /* Byte and Halfword Transform */ 283 ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT; 284 285 /* Rxd Sample Delay */ 286 ctrlr0 |= 0 << RXDSD_SHIFT; 287 288 /* Frame Format */ 289 ctrlr0 |= FRF_SPI << FRF_SHIFT; 290 291 /* Tx and Rx mode */ 292 ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT; 293 294 writel(ctrlr0, ®s->ctrlr0); 295 296 return 0; 297 } 298 299 static int rockchip_spi_release_bus(struct udevice *dev) 300 { 301 struct udevice *bus = dev->parent; 302 struct rockchip_spi_priv *priv = dev_get_priv(bus); 303 304 rkspi_enable_chip(priv->regs, false); 305 306 return 0; 307 } 308 309 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, 310 const void *dout, void *din, unsigned long flags) 311 { 312 struct udevice *bus = dev->parent; 313 struct rockchip_spi_priv *priv = dev_get_priv(bus); 314 struct rockchip_spi *regs = priv->regs; 315 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 316 int len = bitlen >> 3; 317 const u8 *out = dout; 318 u8 *in = din; 319 int toread, towrite; 320 int ret; 321 322 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, 323 len, flags); 324 if (DEBUG_RK_SPI) 325 rkspi_dump_regs(regs); 326 327 /* Assert CS before transfer */ 328 if (flags & SPI_XFER_BEGIN) 329 spi_cs_activate(dev, slave_plat->cs); 330 331 while (len > 0) { 332 int todo = min(len, 0xffff); 333 334 rkspi_enable_chip(regs, false); 335 writel(todo - 1, ®s->ctrlr1); 336 rkspi_enable_chip(regs, true); 337 338 toread = todo; 339 towrite = todo; 340 while (toread || towrite) { 341 u32 status = readl(®s->sr); 342 343 if (towrite && !(status & SR_TF_FULL)) { 344 writel(out ? *out++ : 0, regs->txdr); 345 towrite--; 346 } 347 if (toread && !(status & SR_RF_EMPT)) { 348 u32 byte = readl(regs->rxdr); 349 350 if (in) 351 *in++ = byte; 352 toread--; 353 } 354 } 355 ret = rkspi_wait_till_not_busy(regs); 356 if (ret) 357 break; 358 len -= todo; 359 } 360 361 /* Deassert CS after transfer */ 362 if (flags & SPI_XFER_END) 363 spi_cs_deactivate(dev, slave_plat->cs); 364 365 rkspi_enable_chip(regs, false); 366 367 return ret; 368 } 369 370 static int rockchip_spi_set_speed(struct udevice *bus, uint speed) 371 { 372 struct rockchip_spi_priv *priv = dev_get_priv(bus); 373 374 if (speed > ROCKCHIP_SPI_MAX_RATE) 375 return -EINVAL; 376 if (speed > priv->max_freq) 377 speed = priv->max_freq; 378 priv->speed_hz = speed; 379 380 return 0; 381 } 382 383 static int rockchip_spi_set_mode(struct udevice *bus, uint mode) 384 { 385 struct rockchip_spi_priv *priv = dev_get_priv(bus); 386 387 priv->mode = mode; 388 389 return 0; 390 } 391 392 static const struct dm_spi_ops rockchip_spi_ops = { 393 .claim_bus = rockchip_spi_claim_bus, 394 .release_bus = rockchip_spi_release_bus, 395 .xfer = rockchip_spi_xfer, 396 .set_speed = rockchip_spi_set_speed, 397 .set_mode = rockchip_spi_set_mode, 398 /* 399 * cs_info is not needed, since we require all chip selects to be 400 * in the device tree explicitly 401 */ 402 }; 403 404 static const struct udevice_id rockchip_spi_ids[] = { 405 { .compatible = "rockchip,rk3288-spi" }, 406 { } 407 }; 408 409 U_BOOT_DRIVER(rockchip_spi) = { 410 #if CONFIG_IS_ENABLED(OF_PLATDATA) 411 .name = "rockchip_rk3288_spi", 412 #else 413 .name = "rockchip_spi", 414 #endif 415 .id = UCLASS_SPI, 416 .of_match = rockchip_spi_ids, 417 .ops = &rockchip_spi_ops, 418 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata, 419 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata), 420 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv), 421 .probe = rockchip_spi_probe, 422 }; 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