xref: /openbmc/u-boot/drivers/spi/pl022_spi.c (revision afaea1f5) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2012
4  * Armando Visconti, ST Microelectronics, armando.visconti@st.com.
5  *
6  * (C) Copyright 2018
7  * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
8  *
9  * Driver for ARM PL022 SPI Controller.
10  */
11 
12 #include <asm/io.h>
13 #include <clk.h>
14 #include <common.h>
15 #include <dm.h>
16 #include <dm/platform_data/pl022_spi.h>
17 #include <fdtdec.h>
18 #include <linux/bitops.h>
19 #include <linux/bug.h>
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <spi.h>
23 
24 #define SSP_CR0		0x000
25 #define SSP_CR1		0x004
26 #define SSP_DR		0x008
27 #define SSP_SR		0x00C
28 #define SSP_CPSR	0x010
29 #define SSP_IMSC	0x014
30 #define SSP_RIS		0x018
31 #define SSP_MIS		0x01C
32 #define SSP_ICR		0x020
33 #define SSP_DMACR	0x024
34 #define SSP_CSR		0x030 /* vendor extension */
35 #define SSP_ITCR	0x080
36 #define SSP_ITIP	0x084
37 #define SSP_ITOP	0x088
38 #define SSP_TDR		0x08C
39 
40 #define SSP_PID0	0xFE0
41 #define SSP_PID1	0xFE4
42 #define SSP_PID2	0xFE8
43 #define SSP_PID3	0xFEC
44 
45 #define SSP_CID0	0xFF0
46 #define SSP_CID1	0xFF4
47 #define SSP_CID2	0xFF8
48 #define SSP_CID3	0xFFC
49 
50 /* SSP Control Register 0  - SSP_CR0 */
51 #define SSP_CR0_SPO		(0x1 << 6)
52 #define SSP_CR0_SPH		(0x1 << 7)
53 #define SSP_CR0_BIT_MODE(x)	((x) - 1)
54 #define SSP_SCR_MIN		(0x00)
55 #define SSP_SCR_MAX		(0xFF)
56 #define SSP_SCR_SHFT		8
57 #define DFLT_CLKRATE		2
58 
59 /* SSP Control Register 1  - SSP_CR1 */
60 #define SSP_CR1_MASK_SSE	(0x1 << 1)
61 
62 #define SSP_CPSR_MIN		(0x02)
63 #define SSP_CPSR_MAX		(0xFE)
64 #define DFLT_PRESCALE		(0x40)
65 
66 /* SSP Status Register - SSP_SR */
67 #define SSP_SR_MASK_TFE		(0x1 << 0) /* Transmit FIFO empty */
68 #define SSP_SR_MASK_TNF		(0x1 << 1) /* Transmit FIFO not full */
69 #define SSP_SR_MASK_RNE		(0x1 << 2) /* Receive FIFO not empty */
70 #define SSP_SR_MASK_RFF		(0x1 << 3) /* Receive FIFO full */
71 #define SSP_SR_MASK_BSY		(0x1 << 4) /* Busy Flag */
72 
73 struct pl022_spi_slave {
74 	void *base;
75 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
76 	struct clk clk;
77 #else
78 	unsigned int freq;
79 #endif
80 };
81 
82 /*
83  * ARM PL022 exists in different 'flavors'.
84  * This drivers currently support the standard variant (0x00041022), that has a
85  * 16bit wide and 8 locations deep TX/RX FIFO.
86  */
87 static int pl022_is_supported(struct pl022_spi_slave *ps)
88 {
89 	/* PL022 version is 0x00041022 */
90 	if ((readw(ps->base + SSP_PID0) == 0x22) &&
91 	    (readw(ps->base + SSP_PID1) == 0x10) &&
92 	    ((readw(ps->base + SSP_PID2) & 0xf) == 0x04) &&
93 	    (readw(ps->base + SSP_PID3) == 0x00))
94 		return 1;
95 
96 	return 0;
97 }
98 
99 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
100 static int pl022_spi_ofdata_to_platdata(struct udevice *bus)
101 {
102 	struct pl022_spi_pdata *plat = bus->platdata;
103 	const void *fdt = gd->fdt_blob;
104 	int node = dev_of_offset(bus);
105 
106 	plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size);
107 
108 	return clk_get_by_index(bus, 0, &plat->clk);
109 }
110 #endif
111 
112 static int pl022_spi_probe(struct udevice *bus)
113 {
114 	struct pl022_spi_pdata *plat = dev_get_platdata(bus);
115 	struct pl022_spi_slave *ps = dev_get_priv(bus);
116 
117 	ps->base = ioremap(plat->addr, plat->size);
118 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
119 	ps->clk = plat->clk;
120 #else
121 	ps->freq = plat->freq;
122 #endif
123 
124 	/* Check the PL022 version */
125 	if (!pl022_is_supported(ps))
126 		return -ENOTSUPP;
127 
128 	/* 8 bits per word, high polarity and default clock rate */
129 	writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0);
130 	writew(DFLT_PRESCALE, ps->base + SSP_CPSR);
131 
132 	return 0;
133 }
134 
135 static void flush(struct pl022_spi_slave *ps)
136 {
137 	do {
138 		while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE)
139 			readw(ps->base + SSP_DR);
140 	} while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY);
141 }
142 
143 static int pl022_spi_claim_bus(struct udevice *dev)
144 {
145 	struct udevice *bus = dev->parent;
146 	struct pl022_spi_slave *ps = dev_get_priv(bus);
147 	u16 reg;
148 
149 	/* Enable the SPI hardware */
150 	reg = readw(ps->base + SSP_CR1);
151 	reg |= SSP_CR1_MASK_SSE;
152 	writew(reg, ps->base + SSP_CR1);
153 
154 	flush(ps);
155 
156 	return 0;
157 }
158 
159 static int pl022_spi_release_bus(struct udevice *dev)
160 {
161 	struct udevice *bus = dev->parent;
162 	struct pl022_spi_slave *ps = dev_get_priv(bus);
163 	u16 reg;
164 
165 	flush(ps);
166 
167 	/* Disable the SPI hardware */
168 	reg = readw(ps->base + SSP_CR1);
169 	reg &= ~SSP_CR1_MASK_SSE;
170 	writew(reg, ps->base + SSP_CR1);
171 
172 	return 0;
173 }
174 
175 static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
176 			  const void *dout, void *din, unsigned long flags)
177 {
178 	struct udevice *bus = dev->parent;
179 	struct pl022_spi_slave *ps = dev_get_priv(bus);
180 	u32		len_tx = 0, len_rx = 0, len;
181 	u32		ret = 0;
182 	const u8	*txp = dout;
183 	u8		*rxp = din, value;
184 
185 	if (bitlen == 0)
186 		/* Finish any previously submitted transfers */
187 		return 0;
188 
189 	/*
190 	 * TODO: The controller can do non-multiple-of-8 bit
191 	 * transfers, but this driver currently doesn't support it.
192 	 *
193 	 * It's also not clear how such transfers are supposed to be
194 	 * represented as a stream of bytes...this is a limitation of
195 	 * the current SPI interface.
196 	 */
197 	if (bitlen % 8) {
198 		/* Errors always terminate an ongoing transfer */
199 		flags |= SPI_XFER_END;
200 		return -1;
201 	}
202 
203 	len = bitlen / 8;
204 
205 	while (len_tx < len) {
206 		if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) {
207 			value = txp ? *txp++ : 0;
208 			writew(value, ps->base + SSP_DR);
209 			len_tx++;
210 		}
211 
212 		if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
213 			value = readw(ps->base + SSP_DR);
214 			if (rxp)
215 				*rxp++ = value;
216 			len_rx++;
217 		}
218 	}
219 
220 	while (len_rx < len_tx) {
221 		if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
222 			value = readw(ps->base + SSP_DR);
223 			if (rxp)
224 				*rxp++ = value;
225 			len_rx++;
226 		}
227 	}
228 
229 	return ret;
230 }
231 
232 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
233 {
234 	return rate / (cpsdvsr * (1 + scr));
235 }
236 
237 static int pl022_spi_set_speed(struct udevice *bus, uint speed)
238 {
239 	struct pl022_spi_slave *ps = dev_get_priv(bus);
240 	u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr,
241 	    best_cpsr = cpsr;
242 	u32 min, max, best_freq = 0, tmp;
243 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
244 	u32 rate = clk_get_rate(&ps->clk);
245 #else
246 	u32 rate = ps->freq;
247 #endif
248 	bool found = false;
249 
250 	max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN);
251 	min = spi_rate(rate, SSP_CPSR_MAX, SSP_SCR_MAX);
252 
253 	if (speed > max || speed < min) {
254 		pr_err("Tried to set speed to %dHz but min=%d and max=%d\n",
255 		       speed, min, max);
256 		return -EINVAL;
257 	}
258 
259 	while (cpsr <= SSP_CPSR_MAX && !found) {
260 		while (scr <= SSP_SCR_MAX) {
261 			tmp = spi_rate(rate, cpsr, scr);
262 
263 			if (abs(speed - tmp) < abs(speed - best_freq)) {
264 				best_freq = tmp;
265 				best_cpsr = cpsr;
266 				best_scr = scr;
267 
268 				if (tmp == speed) {
269 					found = true;
270 					break;
271 				}
272 			}
273 
274 			scr++;
275 		}
276 		cpsr += 2;
277 		scr = SSP_SCR_MIN;
278 	}
279 
280 	writew(best_cpsr, ps->base + SSP_CPSR);
281 	cr0 = readw(ps->base + SSP_CR0);
282 	writew(cr0 | (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0);
283 
284 	return 0;
285 }
286 
287 static int pl022_spi_set_mode(struct udevice *bus, uint mode)
288 {
289 	struct pl022_spi_slave *ps = dev_get_priv(bus);
290 	u16 reg;
291 
292 	reg = readw(ps->base + SSP_CR0);
293 	reg &= ~(SSP_CR0_SPH | SSP_CR0_SPO);
294 	if (mode & SPI_CPHA)
295 		reg |= SSP_CR0_SPH;
296 	if (mode & SPI_CPOL)
297 		reg |= SSP_CR0_SPO;
298 	writew(reg, ps->base + SSP_CR0);
299 
300 	return 0;
301 }
302 
303 static int pl022_cs_info(struct udevice *bus, uint cs,
304 			 struct spi_cs_info *info)
305 {
306 	return 0;
307 }
308 
309 static const struct dm_spi_ops pl022_spi_ops = {
310 	.claim_bus      = pl022_spi_claim_bus,
311 	.release_bus    = pl022_spi_release_bus,
312 	.xfer           = pl022_spi_xfer,
313 	.set_speed      = pl022_spi_set_speed,
314 	.set_mode       = pl022_spi_set_mode,
315 	.cs_info        = pl022_cs_info,
316 };
317 
318 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
319 static const struct udevice_id pl022_spi_ids[] = {
320 	{ .compatible = "arm,pl022-spi" },
321 	{ }
322 };
323 #endif
324 
325 U_BOOT_DRIVER(pl022_spi) = {
326 	.name   = "pl022_spi",
327 	.id     = UCLASS_SPI,
328 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
329 	.of_match = pl022_spi_ids,
330 #endif
331 	.ops    = &pl022_spi_ops,
332 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
333 	.ofdata_to_platdata = pl022_spi_ofdata_to_platdata,
334 #endif
335 	.platdata_auto_alloc_size = sizeof(struct pl022_spi_pdata),
336 	.priv_auto_alloc_size = sizeof(struct pl022_spi_slave),
337 	.probe  = pl022_spi_probe,
338 };
339