1 /* 2 * Microchip PIC32 SPI controller driver. 3 * 4 * Copyright (c) 2015, Microchip Technology Inc. 5 * Purna Chandra Mandal <purna.mandal@microchip.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <clk.h> 12 #include <dm.h> 13 #include <linux/compat.h> 14 #include <malloc.h> 15 #include <spi.h> 16 17 #include <asm/types.h> 18 #include <asm/io.h> 19 #include <asm/gpio.h> 20 #include <dt-bindings/clock/microchip,clock.h> 21 #include <mach/pic32.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 /* PIC32 SPI controller registers */ 26 struct pic32_reg_spi { 27 struct pic32_reg_atomic ctrl; 28 struct pic32_reg_atomic status; 29 struct pic32_reg_atomic buf; 30 struct pic32_reg_atomic baud; 31 struct pic32_reg_atomic ctrl2; 32 }; 33 34 /* Bit fields in SPI Control Register */ 35 #define PIC32_SPI_CTRL_MSTEN BIT(5) /* Enable SPI Master */ 36 #define PIC32_SPI_CTRL_CKP BIT(6) /* active low */ 37 #define PIC32_SPI_CTRL_CKE BIT(8) /* Tx on falling edge */ 38 #define PIC32_SPI_CTRL_SMP BIT(9) /* Rx at middle or end of tx */ 39 #define PIC32_SPI_CTRL_BPW_MASK 0x03 /* Bits per word */ 40 #define PIC32_SPI_CTRL_BPW_8 0x0 41 #define PIC32_SPI_CTRL_BPW_16 0x1 42 #define PIC32_SPI_CTRL_BPW_32 0x2 43 #define PIC32_SPI_CTRL_BPW_SHIFT 10 44 #define PIC32_SPI_CTRL_ON BIT(15) /* Macro enable */ 45 #define PIC32_SPI_CTRL_ENHBUF BIT(16) /* Enable enhanced buffering */ 46 #define PIC32_SPI_CTRL_MCLKSEL BIT(23) /* Select SPI Clock src */ 47 #define PIC32_SPI_CTRL_MSSEN BIT(28) /* SPI macro will drive SS */ 48 #define PIC32_SPI_CTRL_FRMEN BIT(31) /* Enable framing mode */ 49 50 /* Bit fields in SPI Status Register */ 51 #define PIC32_SPI_STAT_RX_OV BIT(6) /* err, s/w needs to clear */ 52 #define PIC32_SPI_STAT_TF_LVL_MASK 0x1f 53 #define PIC32_SPI_STAT_TF_LVL_SHIFT 16 54 #define PIC32_SPI_STAT_RF_LVL_MASK 0x1f 55 #define PIC32_SPI_STAT_RF_LVL_SHIFT 24 56 57 /* Bit fields in SPI Baud Register */ 58 #define PIC32_SPI_BAUD_MASK 0x1ff 59 60 struct pic32_spi_priv { 61 struct pic32_reg_spi *regs; 62 u32 fifo_depth; /* FIFO depth in bytes */ 63 u32 fifo_n_word; /* FIFO depth in words */ 64 struct gpio_desc cs_gpio; 65 66 /* Current SPI slave specific */ 67 ulong clk_rate; 68 u32 speed_hz; /* spi-clk rate */ 69 int mode; 70 71 /* Current message/transfer state */ 72 const void *tx; 73 const void *tx_end; 74 const void *rx; 75 const void *rx_end; 76 u32 len; 77 78 /* SPI FiFo accessor */ 79 void (*rx_fifo)(struct pic32_spi_priv *); 80 void (*tx_fifo)(struct pic32_spi_priv *); 81 }; 82 83 static inline void pic32_spi_enable(struct pic32_spi_priv *priv) 84 { 85 writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set); 86 } 87 88 static inline void pic32_spi_disable(struct pic32_spi_priv *priv) 89 { 90 writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr); 91 } 92 93 static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv) 94 { 95 u32 sr = readl(&priv->regs->status.raw); 96 97 return (sr >> PIC32_SPI_STAT_RF_LVL_SHIFT) & PIC32_SPI_STAT_RF_LVL_MASK; 98 } 99 100 static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv) 101 { 102 u32 sr = readl(&priv->regs->status.raw); 103 104 return (sr >> PIC32_SPI_STAT_TF_LVL_SHIFT) & PIC32_SPI_STAT_TF_LVL_MASK; 105 } 106 107 /* Return the max entries we can fill into tx fifo */ 108 static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes) 109 { 110 u32 tx_left, tx_room, rxtx_gap; 111 112 tx_left = (priv->tx_end - priv->tx) / n_bytes; 113 tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv); 114 115 rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx); 116 rxtx_gap /= n_bytes; 117 return min3(tx_left, tx_room, (u32)(priv->fifo_n_word - rxtx_gap)); 118 } 119 120 /* Return the max entries we should read out of rx fifo */ 121 static u32 pic32_rx_max(struct pic32_spi_priv *priv, int n_bytes) 122 { 123 u32 rx_left = (priv->rx_end - priv->rx) / n_bytes; 124 125 return min_t(u32, rx_left, pic32_spi_rx_fifo_level(priv)); 126 } 127 128 #define BUILD_SPI_FIFO_RW(__name, __type, __bwl) \ 129 static void pic32_spi_rx_##__name(struct pic32_spi_priv *priv) \ 130 { \ 131 __type val; \ 132 u32 mx = pic32_rx_max(priv, sizeof(__type)); \ 133 \ 134 for (; mx; mx--) { \ 135 val = read##__bwl(&priv->regs->buf.raw); \ 136 if (priv->rx_end - priv->len) \ 137 *(__type *)(priv->rx) = val; \ 138 priv->rx += sizeof(__type); \ 139 } \ 140 } \ 141 \ 142 static void pic32_spi_tx_##__name(struct pic32_spi_priv *priv) \ 143 { \ 144 __type val; \ 145 u32 mx = pic32_tx_max(priv, sizeof(__type)); \ 146 \ 147 for (; mx ; mx--) { \ 148 val = (__type) ~0U; \ 149 if (priv->tx_end - priv->len) \ 150 val = *(__type *)(priv->tx); \ 151 write##__bwl(val, &priv->regs->buf.raw); \ 152 priv->tx += sizeof(__type); \ 153 } \ 154 } 155 BUILD_SPI_FIFO_RW(byte, u8, b); 156 BUILD_SPI_FIFO_RW(word, u16, w); 157 BUILD_SPI_FIFO_RW(dword, u32, l); 158 159 static int pic32_spi_set_word_size(struct pic32_spi_priv *priv, 160 unsigned int wordlen) 161 { 162 u32 bits_per_word; 163 u32 val; 164 165 switch (wordlen) { 166 case 8: 167 priv->rx_fifo = pic32_spi_rx_byte; 168 priv->tx_fifo = pic32_spi_tx_byte; 169 bits_per_word = PIC32_SPI_CTRL_BPW_8; 170 break; 171 case 16: 172 priv->rx_fifo = pic32_spi_rx_word; 173 priv->tx_fifo = pic32_spi_tx_word; 174 bits_per_word = PIC32_SPI_CTRL_BPW_16; 175 break; 176 case 32: 177 priv->rx_fifo = pic32_spi_rx_dword; 178 priv->tx_fifo = pic32_spi_tx_dword; 179 bits_per_word = PIC32_SPI_CTRL_BPW_32; 180 break; 181 default: 182 printf("pic32-spi: unsupported wordlen\n"); 183 return -EINVAL; 184 } 185 186 /* set bits-per-word */ 187 val = readl(&priv->regs->ctrl.raw); 188 val &= ~(PIC32_SPI_CTRL_BPW_MASK << PIC32_SPI_CTRL_BPW_SHIFT); 189 val |= bits_per_word << PIC32_SPI_CTRL_BPW_SHIFT; 190 writel(val, &priv->regs->ctrl.raw); 191 192 /* calculate maximum number of words fifo can hold */ 193 priv->fifo_n_word = DIV_ROUND_UP(priv->fifo_depth, wordlen / 8); 194 195 return 0; 196 } 197 198 static int pic32_spi_claim_bus(struct udevice *slave) 199 { 200 struct pic32_spi_priv *priv = dev_get_priv(slave->parent); 201 202 /* enable chip */ 203 pic32_spi_enable(priv); 204 205 return 0; 206 } 207 208 static int pic32_spi_release_bus(struct udevice *slave) 209 { 210 struct pic32_spi_priv *priv = dev_get_priv(slave->parent); 211 212 /* disable chip */ 213 pic32_spi_disable(priv); 214 215 return 0; 216 } 217 218 static void spi_cs_activate(struct pic32_spi_priv *priv) 219 { 220 if (!dm_gpio_is_valid(&priv->cs_gpio)) 221 return; 222 223 dm_gpio_set_value(&priv->cs_gpio, 1); 224 } 225 226 static void spi_cs_deactivate(struct pic32_spi_priv *priv) 227 { 228 if (!dm_gpio_is_valid(&priv->cs_gpio)) 229 return; 230 231 dm_gpio_set_value(&priv->cs_gpio, 0); 232 } 233 234 static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen, 235 const void *tx_buf, void *rx_buf, 236 unsigned long flags) 237 { 238 struct dm_spi_slave_platdata *slave_plat; 239 struct udevice *bus = slave->parent; 240 struct pic32_spi_priv *priv; 241 int len = bitlen / 8; 242 int ret = 0; 243 ulong tbase; 244 245 priv = dev_get_priv(bus); 246 slave_plat = dev_get_parent_platdata(slave); 247 248 debug("spi_xfer: bus:%i cs:%i flags:%lx\n", 249 bus->seq, slave_plat->cs, flags); 250 debug("msg tx %p, rx %p submitted of %d byte(s)\n", 251 tx_buf, rx_buf, len); 252 253 /* assert cs */ 254 if (flags & SPI_XFER_BEGIN) 255 spi_cs_activate(priv); 256 257 /* set current transfer information */ 258 priv->tx = tx_buf; 259 priv->rx = rx_buf; 260 priv->tx_end = priv->tx + len; 261 priv->rx_end = priv->rx + len; 262 priv->len = len; 263 264 /* transact by polling */ 265 tbase = get_timer(0); 266 for (;;) { 267 priv->tx_fifo(priv); 268 priv->rx_fifo(priv); 269 270 /* received sufficient data */ 271 if (priv->rx >= priv->rx_end) { 272 ret = 0; 273 break; 274 } 275 276 if (get_timer(tbase) > 5 * CONFIG_SYS_HZ) { 277 printf("pic32_spi: error, xfer timedout.\n"); 278 flags |= SPI_XFER_END; 279 ret = -ETIMEDOUT; 280 break; 281 } 282 } 283 284 /* deassert cs */ 285 if (flags & SPI_XFER_END) 286 spi_cs_deactivate(priv); 287 288 return ret; 289 } 290 291 static int pic32_spi_set_speed(struct udevice *bus, uint speed) 292 { 293 struct pic32_spi_priv *priv = dev_get_priv(bus); 294 u32 div; 295 296 debug("%s: %s, speed %u\n", __func__, bus->name, speed); 297 298 /* div = [clk_in / (2 * spi_clk)] - 1 */ 299 div = (priv->clk_rate / 2 / speed) - 1; 300 div &= PIC32_SPI_BAUD_MASK; 301 writel(div, &priv->regs->baud.raw); 302 303 priv->speed_hz = speed; 304 305 return 0; 306 } 307 308 static int pic32_spi_set_mode(struct udevice *bus, uint mode) 309 { 310 struct pic32_spi_priv *priv = dev_get_priv(bus); 311 u32 val; 312 313 debug("%s: %s, mode %d\n", __func__, bus->name, mode); 314 315 /* set spi-clk mode */ 316 val = readl(&priv->regs->ctrl.raw); 317 /* HIGH when idle */ 318 if (mode & SPI_CPOL) 319 val |= PIC32_SPI_CTRL_CKP; 320 else 321 val &= ~PIC32_SPI_CTRL_CKP; 322 323 /* TX at idle-to-active clk transition */ 324 if (mode & SPI_CPHA) 325 val &= ~PIC32_SPI_CTRL_CKE; 326 else 327 val |= PIC32_SPI_CTRL_CKE; 328 329 /* RX at end of tx */ 330 val |= PIC32_SPI_CTRL_SMP; 331 writel(val, &priv->regs->ctrl.raw); 332 333 priv->mode = mode; 334 335 return 0; 336 } 337 338 static int pic32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen) 339 { 340 struct pic32_spi_priv *priv = dev_get_priv(slave->parent); 341 342 return pic32_spi_set_word_size(priv, wordlen); 343 } 344 345 static void pic32_spi_hw_init(struct pic32_spi_priv *priv) 346 { 347 u32 val; 348 349 /* disable module */ 350 pic32_spi_disable(priv); 351 352 val = readl(&priv->regs->ctrl); 353 354 /* enable enhanced fifo of 128bit deep */ 355 val |= PIC32_SPI_CTRL_ENHBUF; 356 priv->fifo_depth = 16; 357 358 /* disable framing mode */ 359 val &= ~PIC32_SPI_CTRL_FRMEN; 360 361 /* enable master mode */ 362 val |= PIC32_SPI_CTRL_MSTEN; 363 364 /* select clk source */ 365 val &= ~PIC32_SPI_CTRL_MCLKSEL; 366 367 /* set manual /CS mode */ 368 val &= ~PIC32_SPI_CTRL_MSSEN; 369 370 writel(val, &priv->regs->ctrl); 371 372 /* clear rx overflow indicator */ 373 writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr); 374 } 375 376 static int pic32_spi_probe(struct udevice *bus) 377 { 378 struct pic32_spi_priv *priv = dev_get_priv(bus); 379 struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus); 380 int node = dev_of_offset(bus); 381 struct udevice *clkdev; 382 fdt_addr_t addr; 383 fdt_size_t size; 384 int ret; 385 386 debug("%s: %d, bus: %i\n", __func__, __LINE__, bus->seq); 387 addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size); 388 if (addr == FDT_ADDR_T_NONE) 389 return -EINVAL; 390 391 priv->regs = ioremap(addr, size); 392 if (!priv->regs) 393 return -EINVAL; 394 395 dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency", 396 250000000); 397 /* get clock rate */ 398 ret = clk_get_by_index(bus, 0, &clkdev); 399 if (ret < 0) { 400 printf("pic32-spi: error, clk not found\n"); 401 return ret; 402 } 403 priv->clk_rate = clk_get_periph_rate(clkdev, ret); 404 405 /* initialize HW */ 406 pic32_spi_hw_init(priv); 407 408 /* set word len */ 409 pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN); 410 411 /* PIC32 SPI controller can automatically drive /CS during transfer 412 * depending on fifo fill-level. /CS will stay asserted as long as 413 * TX fifo is non-empty, else will be deasserted confirming completion 414 * of the ongoing transfer. To avoid this sort of error we will drive 415 * /CS manually by toggling cs-gpio pins. 416 */ 417 ret = gpio_request_by_name_nodev(gd->fdt_blob, node, "cs-gpios", 0, 418 &priv->cs_gpio, GPIOD_IS_OUT); 419 if (ret) { 420 printf("pic32-spi: error, cs-gpios not found\n"); 421 return ret; 422 } 423 424 return 0; 425 } 426 427 static const struct dm_spi_ops pic32_spi_ops = { 428 .claim_bus = pic32_spi_claim_bus, 429 .release_bus = pic32_spi_release_bus, 430 .xfer = pic32_spi_xfer, 431 .set_speed = pic32_spi_set_speed, 432 .set_mode = pic32_spi_set_mode, 433 .set_wordlen = pic32_spi_set_wordlen, 434 }; 435 436 static const struct udevice_id pic32_spi_ids[] = { 437 { .compatible = "microchip,pic32mzda-spi" }, 438 { } 439 }; 440 441 U_BOOT_DRIVER(pic32_spi) = { 442 .name = "pic32_spi", 443 .id = UCLASS_SPI, 444 .of_match = pic32_spi_ids, 445 .ops = &pic32_spi_ops, 446 .priv_auto_alloc_size = sizeof(struct pic32_spi_priv), 447 .probe = pic32_spi_probe, 448 }; 449