1 /* 2 * Copyright (C) 2016 Jagan Teki <jteki@openedev.com> 3 * Christophe Ricard <christophe.ricard@gmail.com> 4 * 5 * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com> 6 * 7 * Driver for McSPI controller on OMAP3. Based on davinci_spi.c 8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 9 * 10 * Copyright (C) 2007 Atmel Corporation 11 * 12 * Parts taken from linux/drivers/spi/omap2_mcspi.c 13 * Copyright (C) 2005, 2006 Nokia Corporation 14 * 15 * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com> 16 * 17 * SPDX-License-Identifier: GPL-2.0+ 18 */ 19 20 #include <common.h> 21 #include <dm.h> 22 #include <spi.h> 23 #include <malloc.h> 24 #include <asm/io.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) 29 #define OMAP3_MCSPI1_BASE 0x48030100 30 #define OMAP3_MCSPI2_BASE 0x481A0100 31 #else 32 #define OMAP3_MCSPI1_BASE 0x48098000 33 #define OMAP3_MCSPI2_BASE 0x4809A000 34 #define OMAP3_MCSPI3_BASE 0x480B8000 35 #define OMAP3_MCSPI4_BASE 0x480BA000 36 #endif 37 38 /* per-register bitmasks */ 39 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3) 40 #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) 41 #define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) 42 #define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1) 43 44 #define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0) 45 46 #define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0) 47 #define OMAP3_MCSPI_MODULCTRL_MS BIT(2) 48 #define OMAP3_MCSPI_MODULCTRL_STEST BIT(3) 49 50 #define OMAP3_MCSPI_CHCONF_PHA BIT(0) 51 #define OMAP3_MCSPI_CHCONF_POL BIT(1) 52 #define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2) 53 #define OMAP3_MCSPI_CHCONF_EPOL BIT(6) 54 #define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7) 55 #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) 56 #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) 57 #define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12) 58 #define OMAP3_MCSPI_CHCONF_DMAW BIT(14) 59 #define OMAP3_MCSPI_CHCONF_DMAR BIT(15) 60 #define OMAP3_MCSPI_CHCONF_DPE0 BIT(16) 61 #define OMAP3_MCSPI_CHCONF_DPE1 BIT(17) 62 #define OMAP3_MCSPI_CHCONF_IS BIT(18) 63 #define OMAP3_MCSPI_CHCONF_TURBO BIT(19) 64 #define OMAP3_MCSPI_CHCONF_FORCE BIT(20) 65 66 #define OMAP3_MCSPI_CHSTAT_RXS BIT(0) 67 #define OMAP3_MCSPI_CHSTAT_TXS BIT(1) 68 #define OMAP3_MCSPI_CHSTAT_EOT BIT(2) 69 70 #define OMAP3_MCSPI_CHCTRL_EN BIT(0) 71 #define OMAP3_MCSPI_CHCTRL_DIS (0 << 0) 72 73 #define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0) 74 #define MCSPI_PINDIR_D0_IN_D1_OUT 0 75 #define MCSPI_PINDIR_D0_OUT_D1_IN 1 76 77 #define OMAP3_MCSPI_MAX_FREQ 48000000 78 #define SPI_WAIT_TIMEOUT 10 79 80 /* OMAP3 McSPI registers */ 81 struct mcspi_channel { 82 unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */ 83 unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */ 84 unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */ 85 unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */ 86 unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */ 87 }; 88 89 struct mcspi { 90 unsigned char res1[0x10]; 91 unsigned int sysconfig; /* 0x10 */ 92 unsigned int sysstatus; /* 0x14 */ 93 unsigned int irqstatus; /* 0x18 */ 94 unsigned int irqenable; /* 0x1C */ 95 unsigned int wakeupenable; /* 0x20 */ 96 unsigned int syst; /* 0x24 */ 97 unsigned int modulctrl; /* 0x28 */ 98 struct mcspi_channel channel[4]; 99 /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */ 100 /* channel1: 0x40 - 0x50, bus 0 & 1 */ 101 /* channel2: 0x54 - 0x64, bus 0 & 1 */ 102 /* channel3: 0x68 - 0x78, bus 0 */ 103 }; 104 105 struct omap3_spi_priv { 106 #ifndef CONFIG_DM_SPI 107 struct spi_slave slave; 108 #endif 109 struct mcspi *regs; 110 unsigned int cs; 111 unsigned int freq; 112 unsigned int mode; 113 unsigned int wordlen; 114 unsigned int pin_dir:1; 115 }; 116 117 static void omap3_spi_write_chconf(struct omap3_spi_priv *priv, int val) 118 { 119 writel(val, &priv->regs->channel[priv->cs].chconf); 120 /* Flash post writes to make immediate effect */ 121 readl(&priv->regs->channel[priv->cs].chconf); 122 } 123 124 static void omap3_spi_set_enable(struct omap3_spi_priv *priv, int enable) 125 { 126 writel(enable, &priv->regs->channel[priv->cs].chctrl); 127 /* Flash post writes to make immediate effect */ 128 readl(&priv->regs->channel[priv->cs].chctrl); 129 } 130 131 static int omap3_spi_write(struct omap3_spi_priv *priv, unsigned int len, 132 const void *txp, unsigned long flags) 133 { 134 ulong start; 135 int i, chconf; 136 137 chconf = readl(&priv->regs->channel[priv->cs].chconf); 138 139 /* Enable the channel */ 140 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN); 141 142 chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK); 143 chconf |= (priv->wordlen - 1) << 7; 144 chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY; 145 chconf |= OMAP3_MCSPI_CHCONF_FORCE; 146 omap3_spi_write_chconf(priv, chconf); 147 148 for (i = 0; i < len; i++) { 149 /* wait till TX register is empty (TXS == 1) */ 150 start = get_timer(0); 151 while (!(readl(&priv->regs->channel[priv->cs].chstat) & 152 OMAP3_MCSPI_CHSTAT_TXS)) { 153 if (get_timer(start) > SPI_WAIT_TIMEOUT) { 154 printf("SPI TXS timed out, status=0x%08x\n", 155 readl(&priv->regs->channel[priv->cs].chstat)); 156 return -1; 157 } 158 } 159 /* Write the data */ 160 unsigned int *tx = &priv->regs->channel[priv->cs].tx; 161 if (priv->wordlen > 16) 162 writel(((u32 *)txp)[i], tx); 163 else if (priv->wordlen > 8) 164 writel(((u16 *)txp)[i], tx); 165 else 166 writel(((u8 *)txp)[i], tx); 167 } 168 169 /* wait to finish of transfer */ 170 while ((readl(&priv->regs->channel[priv->cs].chstat) & 171 (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) != 172 (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) 173 ; 174 175 /* Disable the channel otherwise the next immediate RX will get affected */ 176 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS); 177 178 if (flags & SPI_XFER_END) { 179 180 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE; 181 omap3_spi_write_chconf(priv, chconf); 182 } 183 return 0; 184 } 185 186 static int omap3_spi_read(struct omap3_spi_priv *priv, unsigned int len, 187 void *rxp, unsigned long flags) 188 { 189 int i, chconf; 190 ulong start; 191 192 chconf = readl(&priv->regs->channel[priv->cs].chconf); 193 194 /* Enable the channel */ 195 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN); 196 197 chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK); 198 chconf |= (priv->wordlen - 1) << 7; 199 chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY; 200 chconf |= OMAP3_MCSPI_CHCONF_FORCE; 201 omap3_spi_write_chconf(priv, chconf); 202 203 writel(0, &priv->regs->channel[priv->cs].tx); 204 205 for (i = 0; i < len; i++) { 206 start = get_timer(0); 207 /* Wait till RX register contains data (RXS == 1) */ 208 while (!(readl(&priv->regs->channel[priv->cs].chstat) & 209 OMAP3_MCSPI_CHSTAT_RXS)) { 210 if (get_timer(start) > SPI_WAIT_TIMEOUT) { 211 printf("SPI RXS timed out, status=0x%08x\n", 212 readl(&priv->regs->channel[priv->cs].chstat)); 213 return -1; 214 } 215 } 216 217 /* Disable the channel to prevent furher receiving */ 218 if (i == (len - 1)) 219 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS); 220 221 /* Read the data */ 222 unsigned int *rx = &priv->regs->channel[priv->cs].rx; 223 if (priv->wordlen > 16) 224 ((u32 *)rxp)[i] = readl(rx); 225 else if (priv->wordlen > 8) 226 ((u16 *)rxp)[i] = (u16)readl(rx); 227 else 228 ((u8 *)rxp)[i] = (u8)readl(rx); 229 } 230 231 if (flags & SPI_XFER_END) { 232 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE; 233 omap3_spi_write_chconf(priv, chconf); 234 } 235 236 return 0; 237 } 238 239 /*McSPI Transmit Receive Mode*/ 240 static int omap3_spi_txrx(struct omap3_spi_priv *priv, unsigned int len, 241 const void *txp, void *rxp, unsigned long flags) 242 { 243 ulong start; 244 int chconf, i = 0; 245 246 chconf = readl(&priv->regs->channel[priv->cs].chconf); 247 248 /*Enable SPI channel*/ 249 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN); 250 251 /*set TRANSMIT-RECEIVE Mode*/ 252 chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK); 253 chconf |= (priv->wordlen - 1) << 7; 254 chconf |= OMAP3_MCSPI_CHCONF_FORCE; 255 omap3_spi_write_chconf(priv, chconf); 256 257 /*Shift in and out 1 byte at time*/ 258 for (i=0; i < len; i++){ 259 /* Write: wait for TX empty (TXS == 1)*/ 260 start = get_timer(0); 261 while (!(readl(&priv->regs->channel[priv->cs].chstat) & 262 OMAP3_MCSPI_CHSTAT_TXS)) { 263 if (get_timer(start) > SPI_WAIT_TIMEOUT) { 264 printf("SPI TXS timed out, status=0x%08x\n", 265 readl(&priv->regs->channel[priv->cs].chstat)); 266 return -1; 267 } 268 } 269 /* Write the data */ 270 unsigned int *tx = &priv->regs->channel[priv->cs].tx; 271 if (priv->wordlen > 16) 272 writel(((u32 *)txp)[i], tx); 273 else if (priv->wordlen > 8) 274 writel(((u16 *)txp)[i], tx); 275 else 276 writel(((u8 *)txp)[i], tx); 277 278 /*Read: wait for RX containing data (RXS == 1)*/ 279 start = get_timer(0); 280 while (!(readl(&priv->regs->channel[priv->cs].chstat) & 281 OMAP3_MCSPI_CHSTAT_RXS)) { 282 if (get_timer(start) > SPI_WAIT_TIMEOUT) { 283 printf("SPI RXS timed out, status=0x%08x\n", 284 readl(&priv->regs->channel[priv->cs].chstat)); 285 return -1; 286 } 287 } 288 /* Read the data */ 289 unsigned int *rx = &priv->regs->channel[priv->cs].rx; 290 if (priv->wordlen > 16) 291 ((u32 *)rxp)[i] = readl(rx); 292 else if (priv->wordlen > 8) 293 ((u16 *)rxp)[i] = (u16)readl(rx); 294 else 295 ((u8 *)rxp)[i] = (u8)readl(rx); 296 } 297 /* Disable the channel */ 298 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS); 299 300 /*if transfer must be terminated disable the channel*/ 301 if (flags & SPI_XFER_END) { 302 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE; 303 omap3_spi_write_chconf(priv, chconf); 304 } 305 306 return 0; 307 } 308 309 static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen, 310 const void *dout, void *din, unsigned long flags) 311 { 312 unsigned int len; 313 int ret = -1; 314 315 if (priv->wordlen < 4 || priv->wordlen > 32) { 316 printf("omap3_spi: invalid wordlen %d\n", priv->wordlen); 317 return -1; 318 } 319 320 if (bitlen % priv->wordlen) 321 return -1; 322 323 len = bitlen / priv->wordlen; 324 325 if (bitlen == 0) { /* only change CS */ 326 int chconf = readl(&priv->regs->channel[priv->cs].chconf); 327 328 if (flags & SPI_XFER_BEGIN) { 329 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN); 330 chconf |= OMAP3_MCSPI_CHCONF_FORCE; 331 omap3_spi_write_chconf(priv, chconf); 332 } 333 if (flags & SPI_XFER_END) { 334 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE; 335 omap3_spi_write_chconf(priv, chconf); 336 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS); 337 } 338 ret = 0; 339 } else { 340 if (dout != NULL && din != NULL) 341 ret = omap3_spi_txrx(priv, len, dout, din, flags); 342 else if (dout != NULL) 343 ret = omap3_spi_write(priv, len, dout, flags); 344 else if (din != NULL) 345 ret = omap3_spi_read(priv, len, din, flags); 346 } 347 return ret; 348 } 349 350 static void _omap3_spi_set_speed(struct omap3_spi_priv *priv) 351 { 352 uint32_t confr, div = 0; 353 354 confr = readl(&priv->regs->channel[priv->cs].chconf); 355 356 /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */ 357 if (priv->freq) { 358 while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div)) 359 > priv->freq) 360 div++; 361 } else { 362 div = 0xC; 363 } 364 365 /* set clock divisor */ 366 confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK; 367 confr |= div << 2; 368 369 omap3_spi_write_chconf(priv, confr); 370 } 371 372 static void _omap3_spi_set_mode(struct omap3_spi_priv *priv) 373 { 374 uint32_t confr; 375 376 confr = readl(&priv->regs->channel[priv->cs].chconf); 377 378 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS 379 * REVISIT: this controller could support SPI_3WIRE mode. 380 */ 381 if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { 382 confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1); 383 confr |= OMAP3_MCSPI_CHCONF_DPE0; 384 } else { 385 confr &= ~OMAP3_MCSPI_CHCONF_DPE0; 386 confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1; 387 } 388 389 /* set SPI mode 0..3 */ 390 confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA); 391 if (priv->mode & SPI_CPHA) 392 confr |= OMAP3_MCSPI_CHCONF_PHA; 393 if (priv->mode & SPI_CPOL) 394 confr |= OMAP3_MCSPI_CHCONF_POL; 395 396 /* set chipselect polarity; manage with FORCE */ 397 if (!(priv->mode & SPI_CS_HIGH)) 398 confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */ 399 else 400 confr &= ~OMAP3_MCSPI_CHCONF_EPOL; 401 402 /* Transmit & receive mode */ 403 confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; 404 405 omap3_spi_write_chconf(priv, confr); 406 } 407 408 static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv) 409 { 410 unsigned int confr; 411 412 /* McSPI individual channel configuration */ 413 confr = readl(&priv->regs->channel[priv->wordlen].chconf); 414 415 /* wordlength */ 416 confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK; 417 confr |= (priv->wordlen - 1) << 7; 418 419 omap3_spi_write_chconf(priv, confr); 420 } 421 422 static void spi_reset(struct mcspi *regs) 423 { 424 unsigned int tmp; 425 426 writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, ®s->sysconfig); 427 do { 428 tmp = readl(®s->sysstatus); 429 } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE)); 430 431 writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE | 432 OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP | 433 OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, ®s->sysconfig); 434 435 writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, ®s->wakeupenable); 436 } 437 438 static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv) 439 { 440 unsigned int conf; 441 442 spi_reset(priv->regs); 443 444 /* 445 * setup when switching from (reset default) slave mode 446 * to single-channel master mode 447 */ 448 conf = readl(&priv->regs->modulctrl); 449 conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS); 450 conf |= OMAP3_MCSPI_MODULCTRL_SINGLE; 451 452 writel(conf, &priv->regs->modulctrl); 453 454 _omap3_spi_set_mode(priv); 455 _omap3_spi_set_speed(priv); 456 } 457 458 #ifndef CONFIG_DM_SPI 459 460 static inline struct omap3_spi_priv *to_omap3_spi(struct spi_slave *slave) 461 { 462 return container_of(slave, struct omap3_spi_priv, slave); 463 } 464 465 void spi_init(void) 466 { 467 /* do nothing */ 468 } 469 470 void spi_free_slave(struct spi_slave *slave) 471 { 472 struct omap3_spi_priv *priv = to_omap3_spi(slave); 473 474 free(priv); 475 } 476 477 int spi_claim_bus(struct spi_slave *slave) 478 { 479 struct omap3_spi_priv *priv = to_omap3_spi(slave); 480 481 _omap3_spi_claim_bus(priv); 482 _omap3_spi_set_wordlen(priv); 483 _omap3_spi_set_mode(priv); 484 _omap3_spi_set_speed(priv); 485 486 return 0; 487 } 488 489 void spi_release_bus(struct spi_slave *slave) 490 { 491 struct omap3_spi_priv *priv = to_omap3_spi(slave); 492 493 /* Reset the SPI hardware */ 494 spi_reset(priv->regs); 495 } 496 497 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 498 unsigned int max_hz, unsigned int mode) 499 { 500 struct omap3_spi_priv *priv; 501 struct mcspi *regs; 502 503 /* 504 * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules) 505 * with different number of chip selects (CS, channels): 506 * McSPI1 has 4 CS (bus 0, cs 0 - 3) 507 * McSPI2 has 2 CS (bus 1, cs 0 - 1) 508 * McSPI3 has 2 CS (bus 2, cs 0 - 1) 509 * McSPI4 has 1 CS (bus 3, cs 0) 510 */ 511 512 switch (bus) { 513 case 0: 514 regs = (struct mcspi *)OMAP3_MCSPI1_BASE; 515 break; 516 #ifdef OMAP3_MCSPI2_BASE 517 case 1: 518 regs = (struct mcspi *)OMAP3_MCSPI2_BASE; 519 break; 520 #endif 521 #ifdef OMAP3_MCSPI3_BASE 522 case 2: 523 regs = (struct mcspi *)OMAP3_MCSPI3_BASE; 524 break; 525 #endif 526 #ifdef OMAP3_MCSPI4_BASE 527 case 3: 528 regs = (struct mcspi *)OMAP3_MCSPI4_BASE; 529 break; 530 #endif 531 default: 532 printf("SPI error: unsupported bus %i. Supported busses 0 - 3\n", bus); 533 return NULL; 534 } 535 536 if (((bus == 0) && (cs > 3)) || 537 ((bus == 1) && (cs > 1)) || 538 ((bus == 2) && (cs > 1)) || 539 ((bus == 3) && (cs > 0))) { 540 printf("SPI error: unsupported chip select %i on bus %i\n", cs, bus); 541 return NULL; 542 } 543 544 if (max_hz > OMAP3_MCSPI_MAX_FREQ) { 545 printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 Mhz\n", max_hz); 546 return NULL; 547 } 548 549 if (mode > SPI_MODE_3) { 550 printf("SPI error: unsupported SPI mode %i\n", mode); 551 return NULL; 552 } 553 554 priv = spi_alloc_slave(struct omap3_spi_priv, bus, cs); 555 if (!priv) { 556 printf("SPI error: malloc of SPI structure failed\n"); 557 return NULL; 558 } 559 560 priv->regs = regs; 561 priv->cs = cs; 562 priv->freq = max_hz; 563 priv->mode = mode; 564 priv->wordlen = priv->slave.wordlen; 565 #ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED 566 priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; 567 #endif 568 569 return &priv->slave; 570 } 571 572 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 573 const void *dout, void *din, unsigned long flags) 574 { 575 struct omap3_spi_priv *priv = to_omap3_spi(slave); 576 577 return _spi_xfer(priv, bitlen, dout, din, flags); 578 } 579 580 #else 581 582 static int omap3_spi_claim_bus(struct udevice *dev) 583 { 584 struct udevice *bus = dev->parent; 585 struct omap3_spi_priv *priv = dev_get_priv(bus); 586 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 587 588 priv->cs = slave_plat->cs; 589 priv->mode = slave_plat->mode; 590 priv->freq = slave_plat->max_hz; 591 _omap3_spi_claim_bus(priv); 592 593 return 0; 594 } 595 596 static int omap3_spi_release_bus(struct udevice *dev) 597 { 598 struct udevice *bus = dev->parent; 599 struct omap3_spi_priv *priv = dev_get_priv(bus); 600 601 /* Reset the SPI hardware */ 602 spi_reset(priv->regs); 603 604 return 0; 605 } 606 607 static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen) 608 { 609 struct udevice *bus = dev->parent; 610 struct omap3_spi_priv *priv = dev_get_priv(bus); 611 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 612 613 priv->cs = slave_plat->cs; 614 priv->wordlen = wordlen; 615 _omap3_spi_set_wordlen(priv); 616 617 return 0; 618 } 619 620 static int omap3_spi_probe(struct udevice *dev) 621 { 622 struct omap3_spi_priv *priv = dev_get_priv(dev); 623 const void *blob = gd->fdt_blob; 624 int node = dev->of_offset; 625 626 priv->regs = (struct mcspi *)dev_get_addr(dev); 627 priv->pin_dir = fdtdec_get_uint(blob, node, "ti,pindir-d0-out-d1-in", 628 MCSPI_PINDIR_D0_IN_D1_OUT); 629 priv->wordlen = SPI_DEFAULT_WORDLEN; 630 return 0; 631 } 632 633 static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen, 634 const void *dout, void *din, unsigned long flags) 635 { 636 struct udevice *bus = dev->parent; 637 struct omap3_spi_priv *priv = dev_get_priv(bus); 638 639 return _spi_xfer(priv, bitlen, dout, din, flags); 640 } 641 642 static int omap3_spi_set_speed(struct udevice *bus, unsigned int speed) 643 { 644 return 0; 645 } 646 647 static int omap3_spi_set_mode(struct udevice *bus, uint mode) 648 { 649 return 0; 650 } 651 652 static const struct dm_spi_ops omap3_spi_ops = { 653 .claim_bus = omap3_spi_claim_bus, 654 .release_bus = omap3_spi_release_bus, 655 .set_wordlen = omap3_spi_set_wordlen, 656 .xfer = omap3_spi_xfer, 657 .set_speed = omap3_spi_set_speed, 658 .set_mode = omap3_spi_set_mode, 659 /* 660 * cs_info is not needed, since we require all chip selects to be 661 * in the device tree explicitly 662 */ 663 }; 664 665 static const struct udevice_id omap3_spi_ids[] = { 666 { .compatible = "ti,omap2-mcspi" }, 667 { .compatible = "ti,omap4-mcspi" }, 668 { } 669 }; 670 671 U_BOOT_DRIVER(omap3_spi) = { 672 .name = "omap3_spi", 673 .id = UCLASS_SPI, 674 .of_match = omap3_spi_ids, 675 .probe = omap3_spi_probe, 676 .ops = &omap3_spi_ops, 677 .priv_auto_alloc_size = sizeof(struct omap3_spi_priv), 678 .probe = omap3_spi_probe, 679 }; 680 #endif 681