1 /* 2 * Freescale i.MX28 SPI driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 * 22 * NOTE: This driver only supports the SPI-controller chipselects, 23 * GPIO driven chipselects are not supported. 24 */ 25 26 #include <common.h> 27 #include <malloc.h> 28 #include <spi.h> 29 #include <asm/errno.h> 30 #include <asm/io.h> 31 #include <asm/arch/clock.h> 32 #include <asm/arch/imx-regs.h> 33 #include <asm/arch/sys_proto.h> 34 #include <asm/imx-common/dma.h> 35 36 #define MXS_SPI_MAX_TIMEOUT 1000000 37 #define MXS_SPI_PORT_OFFSET 0x2000 38 #define MXS_SSP_CHIPSELECT_MASK 0x00300000 39 #define MXS_SSP_CHIPSELECT_SHIFT 20 40 41 #define MXSSSP_SMALL_TRANSFER 512 42 43 struct mxs_spi_slave { 44 struct spi_slave slave; 45 uint32_t max_khz; 46 uint32_t mode; 47 struct mxs_ssp_regs *regs; 48 }; 49 50 static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave) 51 { 52 return container_of(slave, struct mxs_spi_slave, slave); 53 } 54 55 void spi_init(void) 56 { 57 } 58 59 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 60 { 61 /* MXS SPI: 4 ports and 3 chip selects maximum */ 62 if (!mxs_ssp_bus_id_valid(bus) || cs > 2) 63 return 0; 64 else 65 return 1; 66 } 67 68 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 69 unsigned int max_hz, unsigned int mode) 70 { 71 struct mxs_spi_slave *mxs_slave; 72 struct mxs_ssp_regs *ssp_regs; 73 int reg; 74 75 if (!spi_cs_is_valid(bus, cs)) { 76 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs); 77 return NULL; 78 } 79 80 mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs); 81 if (!mxs_slave) 82 return NULL; 83 84 if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus)) 85 goto err_init; 86 87 mxs_slave->max_khz = max_hz / 1000; 88 mxs_slave->mode = mode; 89 mxs_slave->regs = mxs_ssp_regs_by_bus(bus); 90 ssp_regs = mxs_slave->regs; 91 92 reg = readl(&ssp_regs->hw_ssp_ctrl0); 93 reg &= ~(MXS_SSP_CHIPSELECT_MASK); 94 reg |= cs << MXS_SSP_CHIPSELECT_SHIFT; 95 96 writel(reg, &ssp_regs->hw_ssp_ctrl0); 97 return &mxs_slave->slave; 98 99 err_init: 100 free(mxs_slave); 101 return NULL; 102 } 103 104 void spi_free_slave(struct spi_slave *slave) 105 { 106 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); 107 free(mxs_slave); 108 } 109 110 int spi_claim_bus(struct spi_slave *slave) 111 { 112 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); 113 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; 114 uint32_t reg = 0; 115 116 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 117 118 writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0); 119 120 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS; 121 reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0; 122 reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0; 123 writel(reg, &ssp_regs->hw_ssp_ctrl1); 124 125 writel(0, &ssp_regs->hw_ssp_cmd0); 126 127 mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz); 128 129 return 0; 130 } 131 132 void spi_release_bus(struct spi_slave *slave) 133 { 134 } 135 136 static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs) 137 { 138 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set); 139 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr); 140 } 141 142 static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs) 143 { 144 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr); 145 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set); 146 } 147 148 static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave, 149 char *data, int length, int write, unsigned long flags) 150 { 151 struct mxs_ssp_regs *ssp_regs = slave->regs; 152 153 if (flags & SPI_XFER_BEGIN) 154 mxs_spi_start_xfer(ssp_regs); 155 156 while (length--) { 157 /* We transfer 1 byte */ 158 #if defined(CONFIG_MX23) 159 writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr); 160 writel(1, &ssp_regs->hw_ssp_ctrl0_set); 161 #elif defined(CONFIG_MX28) 162 writel(1, &ssp_regs->hw_ssp_xfer_size); 163 #endif 164 165 if ((flags & SPI_XFER_END) && !length) 166 mxs_spi_end_xfer(ssp_regs); 167 168 if (write) 169 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr); 170 else 171 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set); 172 173 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set); 174 175 if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg, 176 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) { 177 printf("MXS SPI: Timeout waiting for start\n"); 178 return -ETIMEDOUT; 179 } 180 181 if (write) 182 writel(*data++, &ssp_regs->hw_ssp_data); 183 184 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set); 185 186 if (!write) { 187 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg, 188 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) { 189 printf("MXS SPI: Timeout waiting for data\n"); 190 return -ETIMEDOUT; 191 } 192 193 *data = readl(&ssp_regs->hw_ssp_data); 194 data++; 195 } 196 197 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg, 198 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) { 199 printf("MXS SPI: Timeout waiting for finish\n"); 200 return -ETIMEDOUT; 201 } 202 } 203 204 return 0; 205 } 206 207 static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, 208 char *data, int length, int write, unsigned long flags) 209 { 210 const int xfer_max_sz = 0xff00; 211 const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1; 212 struct mxs_ssp_regs *ssp_regs = slave->regs; 213 struct mxs_dma_desc *dp; 214 uint32_t ctrl0; 215 uint32_t cache_data_count; 216 const uint32_t dstart = (uint32_t)data; 217 int dmach; 218 int tl; 219 int ret = 0; 220 221 #if defined(CONFIG_MX23) 222 const int mxs_spi_pio_words = 1; 223 #elif defined(CONFIG_MX28) 224 const int mxs_spi_pio_words = 4; 225 #endif 226 227 ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count); 228 229 memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count); 230 231 ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0); 232 ctrl0 |= SSP_CTRL0_DATA_XFER; 233 234 if (flags & SPI_XFER_BEGIN) 235 ctrl0 |= SSP_CTRL0_LOCK_CS; 236 if (!write) 237 ctrl0 |= SSP_CTRL0_READ; 238 239 if (length % ARCH_DMA_MINALIGN) 240 cache_data_count = roundup(length, ARCH_DMA_MINALIGN); 241 else 242 cache_data_count = length; 243 244 /* Flush data to DRAM so DMA can pick them up */ 245 if (write) 246 flush_dcache_range(dstart, dstart + cache_data_count); 247 248 /* Invalidate the area, so no writeback into the RAM races with DMA */ 249 invalidate_dcache_range(dstart, dstart + cache_data_count); 250 251 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus; 252 253 dp = desc; 254 while (length) { 255 dp->address = (dma_addr_t)dp; 256 dp->cmd.address = (dma_addr_t)data; 257 258 /* 259 * This is correct, even though it does indeed look insane. 260 * I hereby have to, wholeheartedly, thank Freescale Inc., 261 * for always inventing insane hardware and keeping me busy 262 * and employed ;-) 263 */ 264 if (write) 265 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 266 else 267 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 268 269 /* 270 * The DMA controller can transfer large chunks (64kB) at 271 * time by setting the transfer length to 0. Setting tl to 272 * 0x10000 will overflow below and make .data contain 0. 273 * Otherwise, 0xff00 is the transfer maximum. 274 */ 275 if (length >= 0x10000) 276 tl = 0x10000; 277 else 278 tl = min(length, xfer_max_sz); 279 280 dp->cmd.data |= 281 ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) | 282 (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) | 283 MXS_DMA_DESC_HALT_ON_TERMINATE | 284 MXS_DMA_DESC_TERMINATE_FLUSH; 285 286 data += tl; 287 length -= tl; 288 289 if (!length) { 290 dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM; 291 292 if (flags & SPI_XFER_END) { 293 ctrl0 &= ~SSP_CTRL0_LOCK_CS; 294 ctrl0 |= SSP_CTRL0_IGNORE_CRC; 295 } 296 } 297 298 /* 299 * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in 300 * case of MX28, write only CTRL0 in case of MX23 due 301 * to the difference in register layout. It is utterly 302 * essential that the XFER_SIZE register is written on 303 * a per-descriptor basis with the same size as is the 304 * descriptor! 305 */ 306 dp->cmd.pio_words[0] = ctrl0; 307 #ifdef CONFIG_MX28 308 dp->cmd.pio_words[1] = 0; 309 dp->cmd.pio_words[2] = 0; 310 dp->cmd.pio_words[3] = tl; 311 #endif 312 313 mxs_dma_desc_append(dmach, dp); 314 315 dp++; 316 } 317 318 if (mxs_dma_go(dmach)) 319 ret = -EINVAL; 320 321 /* The data arrived into DRAM, invalidate cache over them */ 322 if (!write) 323 invalidate_dcache_range(dstart, dstart + cache_data_count); 324 325 return ret; 326 } 327 328 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 329 const void *dout, void *din, unsigned long flags) 330 { 331 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); 332 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; 333 int len = bitlen / 8; 334 char dummy; 335 int write = 0; 336 char *data = NULL; 337 int dma = 1; 338 339 if (bitlen == 0) { 340 if (flags & SPI_XFER_END) { 341 din = (void *)&dummy; 342 len = 1; 343 } else 344 return 0; 345 } 346 347 /* Half-duplex only */ 348 if (din && dout) 349 return -EINVAL; 350 /* No data */ 351 if (!din && !dout) 352 return 0; 353 354 if (dout) { 355 data = (char *)dout; 356 write = 1; 357 } else if (din) { 358 data = (char *)din; 359 write = 0; 360 } 361 362 /* 363 * Check for alignment, if the buffer is aligned, do DMA transfer, 364 * PIO otherwise. This is a temporary workaround until proper bounce 365 * buffer is in place. 366 */ 367 if (dma) { 368 if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1)) 369 dma = 0; 370 if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1)) 371 dma = 0; 372 } 373 374 if (!dma || (len < MXSSSP_SMALL_TRANSFER)) { 375 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); 376 return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags); 377 } else { 378 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); 379 return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags); 380 } 381 } 382