1 /* 2 * Freescale i.MX28 SPI driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 * 22 * NOTE: This driver only supports the SPI-controller chipselects, 23 * GPIO driven chipselects are not supported. 24 */ 25 26 #include <common.h> 27 #include <malloc.h> 28 #include <spi.h> 29 #include <asm/errno.h> 30 #include <asm/io.h> 31 #include <asm/arch/clock.h> 32 #include <asm/arch/imx-regs.h> 33 #include <asm/arch/sys_proto.h> 34 #include <asm/arch/dma.h> 35 36 #define MXS_SPI_MAX_TIMEOUT 1000000 37 #define MXS_SPI_PORT_OFFSET 0x2000 38 #define MXS_SSP_CHIPSELECT_MASK 0x00300000 39 #define MXS_SSP_CHIPSELECT_SHIFT 20 40 41 #define MXSSSP_SMALL_TRANSFER 512 42 43 /* 44 * CONFIG_MXS_SPI_DMA_ENABLE: Experimental mixed PIO/DMA support for MXS SPI 45 * host. Use with utmost caution! 46 * 47 * Enabling this is not yet recommended since this 48 * still doesn't support transfers to/from unaligned 49 * addresses. Therefore this driver will not work 50 * for example with saving environment. This is 51 * caused by DMA alignment constraints on MXS. 52 */ 53 54 struct mxs_spi_slave { 55 struct spi_slave slave; 56 uint32_t max_khz; 57 uint32_t mode; 58 struct mxs_ssp_regs *regs; 59 }; 60 61 static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave) 62 { 63 return container_of(slave, struct mxs_spi_slave, slave); 64 } 65 66 void spi_init(void) 67 { 68 } 69 70 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 71 { 72 /* MXS SPI: 4 ports and 3 chip selects maximum */ 73 if (bus > 3 || cs > 2) 74 return 0; 75 else 76 return 1; 77 } 78 79 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 80 unsigned int max_hz, unsigned int mode) 81 { 82 struct mxs_spi_slave *mxs_slave; 83 uint32_t addr; 84 struct mxs_ssp_regs *ssp_regs; 85 int reg; 86 87 if (!spi_cs_is_valid(bus, cs)) { 88 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs); 89 return NULL; 90 } 91 92 mxs_slave = calloc(sizeof(struct mxs_spi_slave), 1); 93 if (!mxs_slave) 94 return NULL; 95 96 if (mxs_dma_init_channel(bus)) 97 goto err_init; 98 99 addr = MXS_SSP0_BASE + (bus * MXS_SPI_PORT_OFFSET); 100 101 mxs_slave->slave.bus = bus; 102 mxs_slave->slave.cs = cs; 103 mxs_slave->max_khz = max_hz / 1000; 104 mxs_slave->mode = mode; 105 mxs_slave->regs = (struct mxs_ssp_regs *)addr; 106 ssp_regs = mxs_slave->regs; 107 108 reg = readl(&ssp_regs->hw_ssp_ctrl0); 109 reg &= ~(MXS_SSP_CHIPSELECT_MASK); 110 reg |= cs << MXS_SSP_CHIPSELECT_SHIFT; 111 112 writel(reg, &ssp_regs->hw_ssp_ctrl0); 113 return &mxs_slave->slave; 114 115 err_init: 116 free(mxs_slave); 117 return NULL; 118 } 119 120 void spi_free_slave(struct spi_slave *slave) 121 { 122 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); 123 free(mxs_slave); 124 } 125 126 int spi_claim_bus(struct spi_slave *slave) 127 { 128 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); 129 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; 130 uint32_t reg = 0; 131 132 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 133 134 writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0); 135 136 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS; 137 reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0; 138 reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0; 139 writel(reg, &ssp_regs->hw_ssp_ctrl1); 140 141 writel(0, &ssp_regs->hw_ssp_cmd0); 142 143 mx28_set_ssp_busclock(slave->bus, mxs_slave->max_khz); 144 145 return 0; 146 } 147 148 void spi_release_bus(struct spi_slave *slave) 149 { 150 } 151 152 static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs) 153 { 154 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set); 155 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr); 156 } 157 158 static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs) 159 { 160 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr); 161 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set); 162 } 163 164 static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave, 165 char *data, int length, int write, unsigned long flags) 166 { 167 struct mxs_ssp_regs *ssp_regs = slave->regs; 168 169 if (flags & SPI_XFER_BEGIN) 170 mxs_spi_start_xfer(ssp_regs); 171 172 while (length--) { 173 /* We transfer 1 byte */ 174 writel(1, &ssp_regs->hw_ssp_xfer_size); 175 176 if ((flags & SPI_XFER_END) && !length) 177 mxs_spi_end_xfer(ssp_regs); 178 179 if (write) 180 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr); 181 else 182 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set); 183 184 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set); 185 186 if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg, 187 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) { 188 printf("MXS SPI: Timeout waiting for start\n"); 189 return -ETIMEDOUT; 190 } 191 192 if (write) 193 writel(*data++, &ssp_regs->hw_ssp_data); 194 195 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set); 196 197 if (!write) { 198 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg, 199 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) { 200 printf("MXS SPI: Timeout waiting for data\n"); 201 return -ETIMEDOUT; 202 } 203 204 *data = readl(&ssp_regs->hw_ssp_data); 205 data++; 206 } 207 208 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg, 209 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) { 210 printf("MXS SPI: Timeout waiting for finish\n"); 211 return -ETIMEDOUT; 212 } 213 } 214 215 return 0; 216 } 217 218 static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, 219 char *data, int length, int write, unsigned long flags) 220 { 221 const int xfer_max_sz = 0xff00; 222 const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1; 223 struct mxs_ssp_regs *ssp_regs = slave->regs; 224 struct mxs_dma_desc *dp; 225 uint32_t ctrl0; 226 uint32_t cache_data_count; 227 int dmach; 228 int tl; 229 230 ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count); 231 232 memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count); 233 234 ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0); 235 ctrl0 |= SSP_CTRL0_DATA_XFER; 236 237 if (flags & SPI_XFER_BEGIN) 238 ctrl0 |= SSP_CTRL0_LOCK_CS; 239 if (!write) 240 ctrl0 |= SSP_CTRL0_READ; 241 242 writel(length, &ssp_regs->hw_ssp_xfer_size); 243 244 if (length % ARCH_DMA_MINALIGN) 245 cache_data_count = roundup(length, ARCH_DMA_MINALIGN); 246 else 247 cache_data_count = length; 248 249 if (write) 250 /* Flush data to DRAM so DMA can pick them up */ 251 flush_dcache_range((uint32_t)data, 252 (uint32_t)(data + cache_data_count)); 253 254 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus; 255 256 dp = desc; 257 while (length) { 258 dp->address = (dma_addr_t)dp; 259 dp->cmd.address = (dma_addr_t)data; 260 261 /* 262 * This is correct, even though it does indeed look insane. 263 * I hereby have to, wholeheartedly, thank Freescale Inc., 264 * for always inventing insane hardware and keeping me busy 265 * and employed ;-) 266 */ 267 if (write) 268 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 269 else 270 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 271 272 /* 273 * The DMA controller can transfer large chunks (64kB) at 274 * time by setting the transfer length to 0. Setting tl to 275 * 0x10000 will overflow below and make .data contain 0. 276 * Otherwise, 0xff00 is the transfer maximum. 277 */ 278 if (length >= 0x10000) 279 tl = 0x10000; 280 else 281 tl = min(length, xfer_max_sz); 282 283 dp->cmd.data |= 284 (tl << MXS_DMA_DESC_BYTES_OFFSET) | 285 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | 286 MXS_DMA_DESC_HALT_ON_TERMINATE | 287 MXS_DMA_DESC_TERMINATE_FLUSH; 288 dp->cmd.pio_words[0] = ctrl0; 289 290 data += tl; 291 length -= tl; 292 293 mxs_dma_desc_append(dmach, dp); 294 295 dp++; 296 } 297 298 dp->address = (dma_addr_t)dp; 299 dp->cmd.address = (dma_addr_t)0; 300 dp->cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | 301 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | 302 MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM; 303 if (flags & SPI_XFER_END) { 304 ctrl0 &= ~SSP_CTRL0_LOCK_CS; 305 dp->cmd.pio_words[0] = ctrl0 | SSP_CTRL0_IGNORE_CRC; 306 } 307 mxs_dma_desc_append(dmach, dp); 308 309 if (mxs_dma_go(dmach)) 310 return -EINVAL; 311 312 /* The data arrived into DRAM, invalidate cache over them */ 313 if (!write) { 314 invalidate_dcache_range((uint32_t)data, 315 (uint32_t)(data + cache_data_count)); 316 } 317 318 return 0; 319 } 320 321 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 322 const void *dout, void *din, unsigned long flags) 323 { 324 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); 325 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; 326 int len = bitlen / 8; 327 char dummy; 328 int write = 0; 329 char *data = NULL; 330 331 #ifdef CONFIG_MXS_SPI_DMA_ENABLE 332 int dma = 1; 333 #else 334 int dma = 0; 335 #endif 336 337 if (bitlen == 0) { 338 if (flags & SPI_XFER_END) { 339 din = (void *)&dummy; 340 len = 1; 341 } else 342 return 0; 343 } 344 345 /* Half-duplex only */ 346 if (din && dout) 347 return -EINVAL; 348 /* No data */ 349 if (!din && !dout) 350 return 0; 351 352 if (dout) { 353 data = (char *)dout; 354 write = 1; 355 } else if (din) { 356 data = (char *)din; 357 write = 0; 358 } 359 360 /* 361 * Check for alignment, if the buffer is aligned, do DMA transfer, 362 * PIO otherwise. This is a temporary workaround until proper bounce 363 * buffer is in place. 364 */ 365 if (dma) { 366 if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1)) 367 dma = 0; 368 if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1)) 369 dma = 0; 370 } 371 372 if (!dma || (len < MXSSSP_SMALL_TRANSFER)) { 373 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); 374 return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags); 375 } else { 376 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); 377 return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags); 378 } 379 } 380