1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #include <common.h> 22 #include <malloc.h> 23 #include <spi.h> 24 #include <asm/errno.h> 25 #include <asm/io.h> 26 #include <mxc_gpio.h> 27 28 #ifdef CONFIG_MX27 29 /* i.MX27 has a completely wrong register layout and register definitions in the 30 * datasheet, the correct one is in the Freescale's Linux driver */ 31 32 #error "i.MX27 CSPI not supported due to drastic differences in register definisions" \ 33 "See linux mxc_spi driver from Freescale for details." 34 35 #elif defined(CONFIG_MX31) 36 37 #include <asm/arch/mx31.h> 38 39 #define MXC_CSPICTRL_EN (1 << 0) 40 #define MXC_CSPICTRL_MODE (1 << 1) 41 #define MXC_CSPICTRL_XCH (1 << 2) 42 #define MXC_CSPICTRL_SMC (1 << 3) 43 #define MXC_CSPICTRL_POL (1 << 4) 44 #define MXC_CSPICTRL_PHA (1 << 5) 45 #define MXC_CSPICTRL_SSCTL (1 << 6) 46 #define MXC_CSPICTRL_SSPOL (1 << 7) 47 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) 48 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) 49 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) 50 #define MXC_CSPICTRL_TC (1 << 8) 51 #define MXC_CSPICTRL_RXOVF (1 << 6) 52 #define MXC_CSPICTRL_MAXBITS 0x1f 53 54 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 55 #define MAX_SPI_BYTES 4 56 57 static unsigned long spi_bases[] = { 58 0x43fa4000, 59 0x50010000, 60 0x53f84000, 61 }; 62 63 #define mxc_get_clock(x) mx31_get_ipg_clk() 64 65 #elif defined(CONFIG_MX51) 66 #include <asm/arch/imx-regs.h> 67 #include <asm/arch/clock.h> 68 69 #define MXC_CSPICTRL_EN (1 << 0) 70 #define MXC_CSPICTRL_MODE (1 << 1) 71 #define MXC_CSPICTRL_XCH (1 << 2) 72 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 73 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 74 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 75 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 76 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 77 #define MXC_CSPICTRL_MAXBITS 0xfff 78 #define MXC_CSPICTRL_TC (1 << 7) 79 #define MXC_CSPICTRL_RXOVF (1 << 6) 80 81 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 82 #define MAX_SPI_BYTES 32 83 84 /* Bit position inside CTRL register to be associated with SS */ 85 #define MXC_CSPICTRL_CHAN 18 86 87 /* Bit position inside CON register to be associated with SS */ 88 #define MXC_CSPICON_POL 4 89 #define MXC_CSPICON_PHA 0 90 #define MXC_CSPICON_SSPOL 12 91 92 static unsigned long spi_bases[] = { 93 CSPI1_BASE_ADDR, 94 CSPI2_BASE_ADDR, 95 CSPI3_BASE_ADDR, 96 }; 97 98 #elif defined(CONFIG_MX35) 99 100 #include <asm/arch/imx-regs.h> 101 #include <asm/arch/clock.h> 102 103 #define MXC_CSPICTRL_EN (1 << 0) 104 #define MXC_CSPICTRL_MODE (1 << 1) 105 #define MXC_CSPICTRL_XCH (1 << 2) 106 #define MXC_CSPICTRL_SMC (1 << 3) 107 #define MXC_CSPICTRL_POL (1 << 4) 108 #define MXC_CSPICTRL_PHA (1 << 5) 109 #define MXC_CSPICTRL_SSCTL (1 << 6) 110 #define MXC_CSPICTRL_SSPOL (1 << 7) 111 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 112 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 113 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) 114 #define MXC_CSPICTRL_TC (1 << 7) 115 #define MXC_CSPICTRL_RXOVF (1 << 6) 116 #define MXC_CSPICTRL_MAXBITS 0xfff 117 118 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 119 #define MAX_SPI_BYTES 4 120 121 static unsigned long spi_bases[] = { 122 0x43fa4000, 123 0x50010000, 124 }; 125 126 #else 127 #error "Unsupported architecture" 128 #endif 129 130 #define OUT MXC_GPIO_DIRECTION_OUT 131 132 #define reg_read readl 133 #define reg_write(a, v) writel(v, a) 134 135 struct mxc_spi_slave { 136 struct spi_slave slave; 137 unsigned long base; 138 u32 ctrl_reg; 139 #if defined(CONFIG_MX51) 140 u32 cfg_reg; 141 #endif 142 int gpio; 143 int ss_pol; 144 }; 145 146 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) 147 { 148 return container_of(slave, struct mxc_spi_slave, slave); 149 } 150 151 void spi_cs_activate(struct spi_slave *slave) 152 { 153 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 154 if (mxcs->gpio > 0) 155 mxc_gpio_set(mxcs->gpio, mxcs->ss_pol); 156 } 157 158 void spi_cs_deactivate(struct spi_slave *slave) 159 { 160 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 161 if (mxcs->gpio > 0) 162 mxc_gpio_set(mxcs->gpio, 163 !(mxcs->ss_pol)); 164 } 165 166 u32 get_cspi_div(u32 div) 167 { 168 int i; 169 170 for (i = 0; i < 8; i++) { 171 if (div <= (4 << i)) 172 return i; 173 } 174 return i; 175 } 176 177 #if defined(CONFIG_MX31) || defined(CONFIG_MX35) 178 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 179 unsigned int max_hz, unsigned int mode) 180 { 181 unsigned int ctrl_reg; 182 u32 clk_src; 183 u32 div; 184 185 clk_src = mxc_get_clock(MXC_CSPI_CLK); 186 187 div = clk_src / max_hz; 188 div = get_cspi_div(div); 189 190 debug("clk %d Hz, div %d, real clk %d Hz\n", 191 max_hz, div, clk_src / (4 << div)); 192 193 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | 194 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | 195 MXC_CSPICTRL_DATARATE(div) | 196 MXC_CSPICTRL_EN | 197 #ifdef CONFIG_MX35 198 MXC_CSPICTRL_SSCTL | 199 #endif 200 MXC_CSPICTRL_MODE; 201 202 if (mode & SPI_CPHA) 203 ctrl_reg |= MXC_CSPICTRL_PHA; 204 if (mode & SPI_CPOL) 205 ctrl_reg |= MXC_CSPICTRL_POL; 206 if (mode & SPI_CS_HIGH) 207 ctrl_reg |= MXC_CSPICTRL_SSPOL; 208 mxcs->ctrl_reg = ctrl_reg; 209 210 return 0; 211 } 212 #endif 213 214 #if defined(CONFIG_MX51) 215 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 216 unsigned int max_hz, unsigned int mode) 217 { 218 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); 219 s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config; 220 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0; 221 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 222 223 if (max_hz == 0) { 224 printf("Error: desired clock is 0\n"); 225 return -1; 226 } 227 228 reg_ctrl = reg_read(®s->ctrl); 229 230 /* Reset spi */ 231 reg_write(®s->ctrl, 0); 232 reg_write(®s->ctrl, (reg_ctrl | 0x1)); 233 234 /* 235 * The following computation is taken directly from Freescale's code. 236 */ 237 if (clk_src > max_hz) { 238 pre_div = clk_src / max_hz; 239 if (pre_div > 16) { 240 post_div = pre_div / 16; 241 pre_div = 15; 242 } 243 if (post_div != 0) { 244 for (i = 0; i < 16; i++) { 245 if ((1 << i) >= post_div) 246 break; 247 } 248 if (i == 16) { 249 printf("Error: no divider for the freq: %d\n", 250 max_hz); 251 return -1; 252 } 253 post_div = i; 254 } 255 } 256 257 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); 258 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | 259 MXC_CSPICTRL_SELCHAN(cs); 260 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | 261 MXC_CSPICTRL_PREDIV(pre_div); 262 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | 263 MXC_CSPICTRL_POSTDIV(post_div); 264 265 /* always set to master mode */ 266 reg_ctrl |= 1 << (cs + 4); 267 268 /* We need to disable SPI before changing registers */ 269 reg_ctrl &= ~MXC_CSPICTRL_EN; 270 271 if (mode & SPI_CS_HIGH) 272 ss_pol = 1; 273 274 if (mode & SPI_CPOL) 275 sclkpol = 1; 276 277 if (mode & SPI_CPHA) 278 sclkpha = 1; 279 280 reg_config = reg_read(®s->cfg); 281 282 /* 283 * Configuration register setup 284 * The MX51 supports different setup for each SS 285 */ 286 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | 287 (ss_pol << (cs + MXC_CSPICON_SSPOL)); 288 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | 289 (sclkpol << (cs + MXC_CSPICON_POL)); 290 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | 291 (sclkpha << (cs + MXC_CSPICON_PHA)); 292 293 debug("reg_ctrl = 0x%x\n", reg_ctrl); 294 reg_write(®s->ctrl, reg_ctrl); 295 debug("reg_config = 0x%x\n", reg_config); 296 reg_write(®s->cfg, reg_config); 297 298 /* save config register and control register */ 299 mxcs->ctrl_reg = reg_ctrl; 300 mxcs->cfg_reg = reg_config; 301 302 /* clear interrupt reg */ 303 reg_write(®s->intr, 0); 304 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 305 306 return 0; 307 } 308 #endif 309 310 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, 311 const u8 *dout, u8 *din, unsigned long flags) 312 { 313 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 314 int nbytes = (bitlen + 7) / 8; 315 u32 data, cnt, i; 316 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 317 318 debug("%s: bitlen %d dout 0x%x din 0x%x\n", 319 __func__, bitlen, (u32)dout, (u32)din); 320 321 mxcs->ctrl_reg = (mxcs->ctrl_reg & 322 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | 323 MXC_CSPICTRL_BITCOUNT(bitlen - 1); 324 325 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); 326 #ifdef CONFIG_MX51 327 reg_write(®s->cfg, mxcs->cfg_reg); 328 #endif 329 330 /* Clear interrupt register */ 331 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 332 333 /* 334 * The SPI controller works only with words, 335 * check if less than a word is sent. 336 * Access to the FIFO is only 32 bit 337 */ 338 if (bitlen % 32) { 339 data = 0; 340 cnt = (bitlen % 32) / 8; 341 if (dout) { 342 for (i = 0; i < cnt; i++) { 343 data = (data << 8) | (*dout++ & 0xFF); 344 } 345 } 346 debug("Sending SPI 0x%x\n", data); 347 348 reg_write(®s->txdata, data); 349 nbytes -= cnt; 350 } 351 352 data = 0; 353 354 while (nbytes > 0) { 355 data = 0; 356 if (dout) { 357 /* Buffer is not 32-bit aligned */ 358 if ((unsigned long)dout & 0x03) { 359 data = 0; 360 for (i = 0; i < 4; i++) 361 data = (data << 8) | (*dout++ & 0xFF); 362 } else { 363 data = *(u32 *)dout; 364 data = cpu_to_be32(data); 365 } 366 dout += 4; 367 } 368 debug("Sending SPI 0x%x\n", data); 369 reg_write(®s->txdata, data); 370 nbytes -= 4; 371 } 372 373 /* FIFO is written, now starts the transfer setting the XCH bit */ 374 reg_write(®s->ctrl, mxcs->ctrl_reg | 375 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); 376 377 /* Wait until the TC (Transfer completed) bit is set */ 378 while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0) 379 ; 380 381 /* Transfer completed, clear any pending request */ 382 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 383 384 nbytes = (bitlen + 7) / 8; 385 386 cnt = nbytes % 32; 387 388 if (bitlen % 32) { 389 data = reg_read(®s->rxdata); 390 cnt = (bitlen % 32) / 8; 391 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); 392 debug("SPI Rx unaligned: 0x%x\n", data); 393 if (din) { 394 memcpy(din, &data, cnt); 395 din += cnt; 396 } 397 nbytes -= cnt; 398 } 399 400 while (nbytes > 0) { 401 u32 tmp; 402 tmp = reg_read(®s->rxdata); 403 data = cpu_to_be32(tmp); 404 debug("SPI Rx: 0x%x 0x%x\n", tmp, data); 405 cnt = min(nbytes, sizeof(data)); 406 if (din) { 407 memcpy(din, &data, cnt); 408 din += cnt; 409 } 410 nbytes -= cnt; 411 } 412 413 return 0; 414 415 } 416 417 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 418 void *din, unsigned long flags) 419 { 420 int n_bytes = (bitlen + 7) / 8; 421 int n_bits; 422 int ret; 423 u32 blk_size; 424 u8 *p_outbuf = (u8 *)dout; 425 u8 *p_inbuf = (u8 *)din; 426 427 if (!slave) 428 return -1; 429 430 if (flags & SPI_XFER_BEGIN) 431 spi_cs_activate(slave); 432 433 while (n_bytes > 0) { 434 if (n_bytes < MAX_SPI_BYTES) 435 blk_size = n_bytes; 436 else 437 blk_size = MAX_SPI_BYTES; 438 439 n_bits = blk_size * 8; 440 441 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); 442 443 if (ret) 444 return ret; 445 if (dout) 446 p_outbuf += blk_size; 447 if (din) 448 p_inbuf += blk_size; 449 n_bytes -= blk_size; 450 } 451 452 if (flags & SPI_XFER_END) { 453 spi_cs_deactivate(slave); 454 } 455 456 return 0; 457 } 458 459 void spi_init(void) 460 { 461 } 462 463 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) 464 { 465 int ret; 466 467 /* 468 * Some SPI devices require active chip-select over multiple 469 * transactions, we achieve this using a GPIO. Still, the SPI 470 * controller has to be configured to use one of its own chipselects. 471 * To use this feature you have to call spi_setup_slave() with 472 * cs = internal_cs | (gpio << 8), and you have to use some unused 473 * on this SPI controller cs between 0 and 3. 474 */ 475 if (cs > 3) { 476 mxcs->gpio = cs >> 8; 477 cs &= 3; 478 ret = mxc_gpio_direction(mxcs->gpio, OUT); 479 if (ret) { 480 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); 481 return -EINVAL; 482 } 483 } else { 484 mxcs->gpio = -1; 485 } 486 487 return cs; 488 } 489 490 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 491 unsigned int max_hz, unsigned int mode) 492 { 493 struct mxc_spi_slave *mxcs; 494 int ret; 495 496 if (bus >= ARRAY_SIZE(spi_bases)) 497 return NULL; 498 499 mxcs = malloc(sizeof(struct mxc_spi_slave)); 500 if (!mxcs) { 501 puts("mxc_spi: SPI Slave not allocated !\n"); 502 return NULL; 503 } 504 505 ret = decode_cs(mxcs, cs); 506 if (ret < 0) { 507 free(mxcs); 508 return NULL; 509 } 510 511 cs = ret; 512 513 mxcs->slave.bus = bus; 514 mxcs->slave.cs = cs; 515 mxcs->base = spi_bases[bus]; 516 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; 517 518 ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); 519 if (ret) { 520 printf("mxc_spi: cannot setup SPI controller\n"); 521 free(mxcs); 522 return NULL; 523 } 524 return &mxcs->slave; 525 } 526 527 void spi_free_slave(struct spi_slave *slave) 528 { 529 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 530 531 free(mxcs); 532 } 533 534 int spi_claim_bus(struct spi_slave *slave) 535 { 536 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 537 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 538 539 reg_write(®s->rxdata, 1); 540 udelay(1); 541 reg_write(®s->ctrl, mxcs->ctrl_reg); 542 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); 543 reg_write(®s->intr, 0); 544 545 return 0; 546 } 547 548 void spi_release_bus(struct spi_slave *slave) 549 { 550 /* TODO: Shut the controller down */ 551 } 552