1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #include <common.h> 22 #include <malloc.h> 23 #include <spi.h> 24 #include <asm/errno.h> 25 #include <asm/io.h> 26 27 #ifdef CONFIG_MX27 28 /* i.MX27 has a completely wrong register layout and register definitions in the 29 * datasheet, the correct one is in the Freescale's Linux driver */ 30 31 #error "i.MX27 CSPI not supported due to drastic differences in register definisions" \ 32 "See linux mxc_spi driver from Freescale for details." 33 34 #elif defined(CONFIG_MX31) 35 36 #include <asm/arch/mx31.h> 37 38 #define MXC_CSPIRXDATA 0x00 39 #define MXC_CSPITXDATA 0x04 40 #define MXC_CSPICTRL 0x08 41 #define MXC_CSPIINT 0x0C 42 #define MXC_CSPIDMA 0x10 43 #define MXC_CSPISTAT 0x14 44 #define MXC_CSPIPERIOD 0x18 45 #define MXC_CSPITEST 0x1C 46 #define MXC_CSPIRESET 0x00 47 48 #define MXC_CSPICTRL_EN (1 << 0) 49 #define MXC_CSPICTRL_MODE (1 << 1) 50 #define MXC_CSPICTRL_XCH (1 << 2) 51 #define MXC_CSPICTRL_SMC (1 << 3) 52 #define MXC_CSPICTRL_POL (1 << 4) 53 #define MXC_CSPICTRL_PHA (1 << 5) 54 #define MXC_CSPICTRL_SSCTL (1 << 6) 55 #define MXC_CSPICTRL_SSPOL (1 << 7) 56 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) 57 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) 58 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) 59 #define MXC_CSPICTRL_TC (1 << 8) 60 #define MXC_CSPICTRL_RXOVF (1 << 6) 61 #define MXC_CSPICTRL_MAXBITS 0x1f 62 63 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 64 65 static unsigned long spi_bases[] = { 66 0x43fa4000, 67 0x50010000, 68 0x53f84000, 69 }; 70 71 #define OUT MX31_GPIO_DIRECTION_OUT 72 #define mxc_gpio_direction mx31_gpio_direction 73 #define mxc_gpio_set mx31_gpio_set 74 #elif defined(CONFIG_MX51) 75 #include <asm/arch/imx-regs.h> 76 #include <asm/arch/clock.h> 77 78 #define MXC_CSPIRXDATA 0x00 79 #define MXC_CSPITXDATA 0x04 80 #define MXC_CSPICTRL 0x08 81 #define MXC_CSPICON 0x0C 82 #define MXC_CSPIINT 0x10 83 #define MXC_CSPIDMA 0x14 84 #define MXC_CSPISTAT 0x18 85 #define MXC_CSPIPERIOD 0x1C 86 #define MXC_CSPIRESET 0x00 87 #define MXC_CSPICTRL_EN (1 << 0) 88 #define MXC_CSPICTRL_MODE (1 << 1) 89 #define MXC_CSPICTRL_XCH (1 << 2) 90 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 91 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 92 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 93 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 94 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 95 #define MXC_CSPICTRL_MAXBITS 0xfff 96 #define MXC_CSPICTRL_TC (1 << 7) 97 #define MXC_CSPICTRL_RXOVF (1 << 6) 98 99 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 100 101 /* Bit position inside CTRL register to be associated with SS */ 102 #define MXC_CSPICTRL_CHAN 18 103 104 /* Bit position inside CON register to be associated with SS */ 105 #define MXC_CSPICON_POL 4 106 #define MXC_CSPICON_PHA 0 107 #define MXC_CSPICON_SSPOL 12 108 109 static unsigned long spi_bases[] = { 110 CSPI1_BASE_ADDR, 111 CSPI2_BASE_ADDR, 112 CSPI3_BASE_ADDR, 113 }; 114 #define mxc_gpio_direction(gpio, dir) (0) 115 #define mxc_gpio_set(gpio, value) {} 116 #define OUT 1 117 #else 118 #error "Unsupported architecture" 119 #endif 120 121 struct mxc_spi_slave { 122 struct spi_slave slave; 123 unsigned long base; 124 u32 ctrl_reg; 125 #if defined(CONFIG_MX51) 126 u32 cfg_reg; 127 #endif 128 int gpio; 129 }; 130 131 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) 132 { 133 return container_of(slave, struct mxc_spi_slave, slave); 134 } 135 136 static inline u32 reg_read(unsigned long addr) 137 { 138 return *(volatile unsigned long*)addr; 139 } 140 141 static inline void reg_write(unsigned long addr, u32 val) 142 { 143 *(volatile unsigned long*)addr = val; 144 } 145 146 void spi_cs_activate(struct spi_slave *slave) 147 { 148 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 149 if (mxcs->gpio > 0) 150 mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL); 151 } 152 153 void spi_cs_deactivate(struct spi_slave *slave) 154 { 155 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 156 if (mxcs->gpio > 0) 157 mxc_gpio_set(mxcs->gpio, 158 !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL)); 159 } 160 161 #ifdef CONFIG_MX51 162 static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, 163 unsigned int max_hz, unsigned int mode) 164 { 165 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); 166 s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config; 167 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0; 168 169 if (max_hz == 0) { 170 printf("Error: desired clock is 0\n"); 171 return -1; 172 } 173 174 reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL); 175 176 /* Reset spi */ 177 reg_write(mxcs->base + MXC_CSPICTRL, 0); 178 reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1)); 179 180 /* 181 * The following computation is taken directly from Freescale's code. 182 */ 183 if (clk_src > max_hz) { 184 pre_div = clk_src / max_hz; 185 if (pre_div > 16) { 186 post_div = pre_div / 16; 187 pre_div = 15; 188 } 189 if (post_div != 0) { 190 for (i = 0; i < 16; i++) { 191 if ((1 << i) >= post_div) 192 break; 193 } 194 if (i == 16) { 195 printf("Error: no divider for the freq: %d\n", 196 max_hz); 197 return -1; 198 } 199 post_div = i; 200 } 201 } 202 203 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); 204 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | 205 MXC_CSPICTRL_SELCHAN(cs); 206 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | 207 MXC_CSPICTRL_PREDIV(pre_div); 208 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | 209 MXC_CSPICTRL_POSTDIV(post_div); 210 211 /* always set to master mode */ 212 reg_ctrl |= 1 << (cs + 4); 213 214 /* We need to disable SPI before changing registers */ 215 reg_ctrl &= ~MXC_CSPICTRL_EN; 216 217 if (mode & SPI_CS_HIGH) 218 ss_pol = 1; 219 220 if (!(mode & SPI_CPOL)) 221 sclkpol = 1; 222 223 if (mode & SPI_CPHA) 224 sclkpha = 1; 225 226 reg_config = reg_read(mxcs->base + MXC_CSPICON); 227 228 /* 229 * Configuration register setup 230 * The MX51 has support different setup for each SS 231 */ 232 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | 233 (ss_pol << (cs + MXC_CSPICON_SSPOL)); 234 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | 235 (sclkpol << (cs + MXC_CSPICON_POL)); 236 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | 237 (sclkpha << (cs + MXC_CSPICON_PHA)); 238 239 debug("reg_ctrl = 0x%x\n", reg_ctrl); 240 reg_write(mxcs->base + MXC_CSPICTRL, reg_ctrl); 241 debug("reg_config = 0x%x\n", reg_config); 242 reg_write(mxcs->base + MXC_CSPICON, reg_config); 243 244 /* save config register and control register */ 245 mxcs->ctrl_reg = reg_ctrl; 246 mxcs->cfg_reg = reg_config; 247 248 /* clear interrupt reg */ 249 reg_write(mxcs->base + MXC_CSPIINT, 0); 250 reg_write(mxcs->base + MXC_CSPISTAT, 251 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 252 253 return 0; 254 } 255 #endif 256 257 static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, 258 unsigned long flags) 259 { 260 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 261 262 if (flags & SPI_XFER_BEGIN) 263 spi_cs_activate(slave); 264 265 mxcs->ctrl_reg = (mxcs->ctrl_reg & 266 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | 267 MXC_CSPICTRL_BITCOUNT(bitlen - 1); 268 269 reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_EN); 270 #ifdef CONFIG_MX51 271 reg_write(mxcs->base + MXC_CSPICON, mxcs->cfg_reg); 272 #endif 273 274 /* Clear interrupt register */ 275 reg_write(mxcs->base + MXC_CSPISTAT, 276 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 277 278 debug("Sending SPI 0x%x\n", data); 279 reg_write(mxcs->base + MXC_CSPITXDATA, data); 280 281 /* FIFO is written, now starts the transfer setting the XCH bit */ 282 reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | 283 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); 284 285 /* Wait until the TC (Transfer completed) bit is set */ 286 while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0) 287 ; 288 289 /* Transfer completed, clear any pending request */ 290 reg_write(mxcs->base + MXC_CSPISTAT, 291 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 292 293 data = reg_read(mxcs->base + MXC_CSPIRXDATA); 294 debug("SPI Rx: 0x%x\n", data); 295 296 if (flags & SPI_XFER_END) 297 spi_cs_deactivate(slave); 298 299 return data; 300 301 } 302 303 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 304 void *din, unsigned long flags) 305 { 306 int n_blks = (bitlen + 31) / 32; 307 u32 *out_l, *in_l; 308 int i; 309 310 if ((int)dout & 3 || (int)din & 3) { 311 printf("Error: unaligned buffers in: %p, out: %p\n", din, dout); 312 return 1; 313 } 314 315 /* This driver is currently partly broken, alert the user */ 316 if (bitlen > 16 && (bitlen % 32)) { 317 printf("Error: SPI transfer with bitlen=%d is broken.\n", 318 bitlen); 319 return 1; 320 } 321 322 for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout; 323 i < n_blks; 324 i++, in_l++, out_l++, bitlen -= 32) { 325 u32 data = spi_xchg_single(slave, *out_l, bitlen, flags); 326 327 /* Check if we're only transfering 8 or 16 bits */ 328 if (!i) { 329 if (bitlen < 9) 330 *(u8 *)din = data; 331 else if (bitlen < 17) 332 *(u16 *)din = data; 333 else 334 *in_l = data; 335 } 336 } 337 338 return 0; 339 } 340 341 void spi_init(void) 342 { 343 } 344 345 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) 346 { 347 int ret; 348 349 /* 350 * Some SPI devices require active chip-select over multiple 351 * transactions, we achieve this using a GPIO. Still, the SPI 352 * controller has to be configured to use one of its own chipselects. 353 * To use this feature you have to call spi_setup_slave() with 354 * cs = internal_cs | (gpio << 8), and you have to use some unused 355 * on this SPI controller cs between 0 and 3. 356 */ 357 if (cs > 3) { 358 mxcs->gpio = cs >> 8; 359 cs &= 3; 360 ret = mxc_gpio_direction(mxcs->gpio, OUT); 361 if (ret) { 362 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); 363 return -EINVAL; 364 } 365 } else { 366 mxcs->gpio = -1; 367 } 368 369 return cs; 370 } 371 372 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 373 unsigned int max_hz, unsigned int mode) 374 { 375 unsigned int ctrl_reg; 376 struct mxc_spi_slave *mxcs; 377 int ret; 378 379 if (bus >= ARRAY_SIZE(spi_bases)) 380 return NULL; 381 382 mxcs = malloc(sizeof(struct mxc_spi_slave)); 383 if (!mxcs) 384 return NULL; 385 386 ret = decode_cs(mxcs, cs); 387 if (ret < 0) { 388 free(mxcs); 389 return NULL; 390 } 391 392 cs = ret; 393 394 mxcs->slave.bus = bus; 395 mxcs->slave.cs = cs; 396 mxcs->base = spi_bases[bus]; 397 398 #ifdef CONFIG_MX51 399 /* Can be used for i.MX31 too ? */ 400 ctrl_reg = 0; 401 ret = spi_cfg(mxcs, cs, max_hz, mode); 402 if (ret) { 403 printf("mxc_spi: cannot setup SPI controller\n"); 404 free(mxcs); 405 return NULL; 406 } 407 #else 408 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | 409 MXC_CSPICTRL_BITCOUNT(31) | 410 MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ 411 MXC_CSPICTRL_EN | 412 MXC_CSPICTRL_MODE; 413 414 if (mode & SPI_CPHA) 415 ctrl_reg |= MXC_CSPICTRL_PHA; 416 if (!(mode & SPI_CPOL)) 417 ctrl_reg |= MXC_CSPICTRL_POL; 418 if (mode & SPI_CS_HIGH) 419 ctrl_reg |= MXC_CSPICTRL_SSPOL; 420 mxcs->ctrl_reg = ctrl_reg; 421 #endif 422 return &mxcs->slave; 423 } 424 425 void spi_free_slave(struct spi_slave *slave) 426 { 427 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 428 429 free(mxcs); 430 } 431 432 int spi_claim_bus(struct spi_slave *slave) 433 { 434 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 435 436 reg_write(mxcs->base + MXC_CSPIRESET, 1); 437 udelay(1); 438 reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg); 439 reg_write(mxcs->base + MXC_CSPIPERIOD, 440 MXC_CSPIPERIOD_32KHZ); 441 reg_write(mxcs->base + MXC_CSPIINT, 0); 442 443 return 0; 444 } 445 446 void spi_release_bus(struct spi_slave *slave) 447 { 448 /* TODO: Shut the controller down */ 449 } 450