1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #include <common.h> 22 #include <malloc.h> 23 #include <spi.h> 24 #include <asm/errno.h> 25 #include <asm/io.h> 26 #include <mxc_gpio.h> 27 #include <asm/arch/imx-regs.h> 28 #include <asm/arch/clock.h> 29 30 #ifdef CONFIG_MX27 31 /* i.MX27 has a completely wrong register layout and register definitions in the 32 * datasheet, the correct one is in the Freescale's Linux driver */ 33 34 #error "i.MX27 CSPI not supported due to drastic differences in register definisions" \ 35 "See linux mxc_spi driver from Freescale for details." 36 37 #elif defined(CONFIG_MX31) 38 39 #define MXC_CSPICTRL_EN (1 << 0) 40 #define MXC_CSPICTRL_MODE (1 << 1) 41 #define MXC_CSPICTRL_XCH (1 << 2) 42 #define MXC_CSPICTRL_SMC (1 << 3) 43 #define MXC_CSPICTRL_POL (1 << 4) 44 #define MXC_CSPICTRL_PHA (1 << 5) 45 #define MXC_CSPICTRL_SSCTL (1 << 6) 46 #define MXC_CSPICTRL_SSPOL (1 << 7) 47 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) 48 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) 49 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) 50 #define MXC_CSPICTRL_TC (1 << 8) 51 #define MXC_CSPICTRL_RXOVF (1 << 6) 52 #define MXC_CSPICTRL_MAXBITS 0x1f 53 54 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 55 #define MAX_SPI_BYTES 4 56 57 static unsigned long spi_bases[] = { 58 0x43fa4000, 59 0x50010000, 60 0x53f84000, 61 }; 62 63 #define mxc_get_clock(x) mx31_get_ipg_clk() 64 65 #elif defined(CONFIG_MX51) 66 67 #define MXC_CSPICTRL_EN (1 << 0) 68 #define MXC_CSPICTRL_MODE (1 << 1) 69 #define MXC_CSPICTRL_XCH (1 << 2) 70 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 71 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 72 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 73 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 74 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 75 #define MXC_CSPICTRL_MAXBITS 0xfff 76 #define MXC_CSPICTRL_TC (1 << 7) 77 #define MXC_CSPICTRL_RXOVF (1 << 6) 78 79 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 80 #define MAX_SPI_BYTES 32 81 82 /* Bit position inside CTRL register to be associated with SS */ 83 #define MXC_CSPICTRL_CHAN 18 84 85 /* Bit position inside CON register to be associated with SS */ 86 #define MXC_CSPICON_POL 4 87 #define MXC_CSPICON_PHA 0 88 #define MXC_CSPICON_SSPOL 12 89 90 static unsigned long spi_bases[] = { 91 CSPI1_BASE_ADDR, 92 CSPI2_BASE_ADDR, 93 CSPI3_BASE_ADDR, 94 }; 95 96 #elif defined(CONFIG_MX35) 97 98 #define MXC_CSPICTRL_EN (1 << 0) 99 #define MXC_CSPICTRL_MODE (1 << 1) 100 #define MXC_CSPICTRL_XCH (1 << 2) 101 #define MXC_CSPICTRL_SMC (1 << 3) 102 #define MXC_CSPICTRL_POL (1 << 4) 103 #define MXC_CSPICTRL_PHA (1 << 5) 104 #define MXC_CSPICTRL_SSCTL (1 << 6) 105 #define MXC_CSPICTRL_SSPOL (1 << 7) 106 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 107 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 108 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) 109 #define MXC_CSPICTRL_TC (1 << 7) 110 #define MXC_CSPICTRL_RXOVF (1 << 6) 111 #define MXC_CSPICTRL_MAXBITS 0xfff 112 113 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 114 #define MAX_SPI_BYTES 4 115 116 static unsigned long spi_bases[] = { 117 0x43fa4000, 118 0x50010000, 119 }; 120 121 #else 122 #error "Unsupported architecture" 123 #endif 124 125 #define OUT MXC_GPIO_DIRECTION_OUT 126 127 #define reg_read readl 128 #define reg_write(a, v) writel(v, a) 129 130 struct mxc_spi_slave { 131 struct spi_slave slave; 132 unsigned long base; 133 u32 ctrl_reg; 134 #if defined(CONFIG_MX51) 135 u32 cfg_reg; 136 #endif 137 int gpio; 138 int ss_pol; 139 }; 140 141 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) 142 { 143 return container_of(slave, struct mxc_spi_slave, slave); 144 } 145 146 void spi_cs_activate(struct spi_slave *slave) 147 { 148 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 149 if (mxcs->gpio > 0) 150 mxc_gpio_set(mxcs->gpio, mxcs->ss_pol); 151 } 152 153 void spi_cs_deactivate(struct spi_slave *slave) 154 { 155 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 156 if (mxcs->gpio > 0) 157 mxc_gpio_set(mxcs->gpio, 158 !(mxcs->ss_pol)); 159 } 160 161 u32 get_cspi_div(u32 div) 162 { 163 int i; 164 165 for (i = 0; i < 8; i++) { 166 if (div <= (4 << i)) 167 return i; 168 } 169 return i; 170 } 171 172 #if defined(CONFIG_MX31) || defined(CONFIG_MX35) 173 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 174 unsigned int max_hz, unsigned int mode) 175 { 176 unsigned int ctrl_reg; 177 u32 clk_src; 178 u32 div; 179 180 clk_src = mxc_get_clock(MXC_CSPI_CLK); 181 182 div = clk_src / max_hz; 183 div = get_cspi_div(div); 184 185 debug("clk %d Hz, div %d, real clk %d Hz\n", 186 max_hz, div, clk_src / (4 << div)); 187 188 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | 189 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | 190 MXC_CSPICTRL_DATARATE(div) | 191 MXC_CSPICTRL_EN | 192 #ifdef CONFIG_MX35 193 MXC_CSPICTRL_SSCTL | 194 #endif 195 MXC_CSPICTRL_MODE; 196 197 if (mode & SPI_CPHA) 198 ctrl_reg |= MXC_CSPICTRL_PHA; 199 if (mode & SPI_CPOL) 200 ctrl_reg |= MXC_CSPICTRL_POL; 201 if (mode & SPI_CS_HIGH) 202 ctrl_reg |= MXC_CSPICTRL_SSPOL; 203 mxcs->ctrl_reg = ctrl_reg; 204 205 return 0; 206 } 207 #endif 208 209 #if defined(CONFIG_MX51) 210 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 211 unsigned int max_hz, unsigned int mode) 212 { 213 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); 214 s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config; 215 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0; 216 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 217 218 if (max_hz == 0) { 219 printf("Error: desired clock is 0\n"); 220 return -1; 221 } 222 223 reg_ctrl = reg_read(®s->ctrl); 224 225 /* Reset spi */ 226 reg_write(®s->ctrl, 0); 227 reg_write(®s->ctrl, (reg_ctrl | 0x1)); 228 229 /* 230 * The following computation is taken directly from Freescale's code. 231 */ 232 if (clk_src > max_hz) { 233 pre_div = clk_src / max_hz; 234 if (pre_div > 16) { 235 post_div = pre_div / 16; 236 pre_div = 15; 237 } 238 if (post_div != 0) { 239 for (i = 0; i < 16; i++) { 240 if ((1 << i) >= post_div) 241 break; 242 } 243 if (i == 16) { 244 printf("Error: no divider for the freq: %d\n", 245 max_hz); 246 return -1; 247 } 248 post_div = i; 249 } 250 } 251 252 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); 253 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | 254 MXC_CSPICTRL_SELCHAN(cs); 255 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | 256 MXC_CSPICTRL_PREDIV(pre_div); 257 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | 258 MXC_CSPICTRL_POSTDIV(post_div); 259 260 /* always set to master mode */ 261 reg_ctrl |= 1 << (cs + 4); 262 263 /* We need to disable SPI before changing registers */ 264 reg_ctrl &= ~MXC_CSPICTRL_EN; 265 266 if (mode & SPI_CS_HIGH) 267 ss_pol = 1; 268 269 if (mode & SPI_CPOL) 270 sclkpol = 1; 271 272 if (mode & SPI_CPHA) 273 sclkpha = 1; 274 275 reg_config = reg_read(®s->cfg); 276 277 /* 278 * Configuration register setup 279 * The MX51 supports different setup for each SS 280 */ 281 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | 282 (ss_pol << (cs + MXC_CSPICON_SSPOL)); 283 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | 284 (sclkpol << (cs + MXC_CSPICON_POL)); 285 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | 286 (sclkpha << (cs + MXC_CSPICON_PHA)); 287 288 debug("reg_ctrl = 0x%x\n", reg_ctrl); 289 reg_write(®s->ctrl, reg_ctrl); 290 debug("reg_config = 0x%x\n", reg_config); 291 reg_write(®s->cfg, reg_config); 292 293 /* save config register and control register */ 294 mxcs->ctrl_reg = reg_ctrl; 295 mxcs->cfg_reg = reg_config; 296 297 /* clear interrupt reg */ 298 reg_write(®s->intr, 0); 299 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 300 301 return 0; 302 } 303 #endif 304 305 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, 306 const u8 *dout, u8 *din, unsigned long flags) 307 { 308 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 309 int nbytes = (bitlen + 7) / 8; 310 u32 data, cnt, i; 311 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 312 313 debug("%s: bitlen %d dout 0x%x din 0x%x\n", 314 __func__, bitlen, (u32)dout, (u32)din); 315 316 mxcs->ctrl_reg = (mxcs->ctrl_reg & 317 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | 318 MXC_CSPICTRL_BITCOUNT(bitlen - 1); 319 320 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); 321 #ifdef CONFIG_MX51 322 reg_write(®s->cfg, mxcs->cfg_reg); 323 #endif 324 325 /* Clear interrupt register */ 326 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 327 328 /* 329 * The SPI controller works only with words, 330 * check if less than a word is sent. 331 * Access to the FIFO is only 32 bit 332 */ 333 if (bitlen % 32) { 334 data = 0; 335 cnt = (bitlen % 32) / 8; 336 if (dout) { 337 for (i = 0; i < cnt; i++) { 338 data = (data << 8) | (*dout++ & 0xFF); 339 } 340 } 341 debug("Sending SPI 0x%x\n", data); 342 343 reg_write(®s->txdata, data); 344 nbytes -= cnt; 345 } 346 347 data = 0; 348 349 while (nbytes > 0) { 350 data = 0; 351 if (dout) { 352 /* Buffer is not 32-bit aligned */ 353 if ((unsigned long)dout & 0x03) { 354 data = 0; 355 for (i = 0; i < 4; i++) 356 data = (data << 8) | (*dout++ & 0xFF); 357 } else { 358 data = *(u32 *)dout; 359 data = cpu_to_be32(data); 360 } 361 dout += 4; 362 } 363 debug("Sending SPI 0x%x\n", data); 364 reg_write(®s->txdata, data); 365 nbytes -= 4; 366 } 367 368 /* FIFO is written, now starts the transfer setting the XCH bit */ 369 reg_write(®s->ctrl, mxcs->ctrl_reg | 370 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); 371 372 /* Wait until the TC (Transfer completed) bit is set */ 373 while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0) 374 ; 375 376 /* Transfer completed, clear any pending request */ 377 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 378 379 nbytes = (bitlen + 7) / 8; 380 381 cnt = nbytes % 32; 382 383 if (bitlen % 32) { 384 data = reg_read(®s->rxdata); 385 cnt = (bitlen % 32) / 8; 386 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); 387 debug("SPI Rx unaligned: 0x%x\n", data); 388 if (din) { 389 memcpy(din, &data, cnt); 390 din += cnt; 391 } 392 nbytes -= cnt; 393 } 394 395 while (nbytes > 0) { 396 u32 tmp; 397 tmp = reg_read(®s->rxdata); 398 data = cpu_to_be32(tmp); 399 debug("SPI Rx: 0x%x 0x%x\n", tmp, data); 400 cnt = min(nbytes, sizeof(data)); 401 if (din) { 402 memcpy(din, &data, cnt); 403 din += cnt; 404 } 405 nbytes -= cnt; 406 } 407 408 return 0; 409 410 } 411 412 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 413 void *din, unsigned long flags) 414 { 415 int n_bytes = (bitlen + 7) / 8; 416 int n_bits; 417 int ret; 418 u32 blk_size; 419 u8 *p_outbuf = (u8 *)dout; 420 u8 *p_inbuf = (u8 *)din; 421 422 if (!slave) 423 return -1; 424 425 if (flags & SPI_XFER_BEGIN) 426 spi_cs_activate(slave); 427 428 while (n_bytes > 0) { 429 if (n_bytes < MAX_SPI_BYTES) 430 blk_size = n_bytes; 431 else 432 blk_size = MAX_SPI_BYTES; 433 434 n_bits = blk_size * 8; 435 436 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); 437 438 if (ret) 439 return ret; 440 if (dout) 441 p_outbuf += blk_size; 442 if (din) 443 p_inbuf += blk_size; 444 n_bytes -= blk_size; 445 } 446 447 if (flags & SPI_XFER_END) { 448 spi_cs_deactivate(slave); 449 } 450 451 return 0; 452 } 453 454 void spi_init(void) 455 { 456 } 457 458 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) 459 { 460 int ret; 461 462 /* 463 * Some SPI devices require active chip-select over multiple 464 * transactions, we achieve this using a GPIO. Still, the SPI 465 * controller has to be configured to use one of its own chipselects. 466 * To use this feature you have to call spi_setup_slave() with 467 * cs = internal_cs | (gpio << 8), and you have to use some unused 468 * on this SPI controller cs between 0 and 3. 469 */ 470 if (cs > 3) { 471 mxcs->gpio = cs >> 8; 472 cs &= 3; 473 ret = mxc_gpio_direction(mxcs->gpio, OUT); 474 if (ret) { 475 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); 476 return -EINVAL; 477 } 478 } else { 479 mxcs->gpio = -1; 480 } 481 482 return cs; 483 } 484 485 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 486 unsigned int max_hz, unsigned int mode) 487 { 488 struct mxc_spi_slave *mxcs; 489 int ret; 490 491 if (bus >= ARRAY_SIZE(spi_bases)) 492 return NULL; 493 494 mxcs = malloc(sizeof(struct mxc_spi_slave)); 495 if (!mxcs) { 496 puts("mxc_spi: SPI Slave not allocated !\n"); 497 return NULL; 498 } 499 500 ret = decode_cs(mxcs, cs); 501 if (ret < 0) { 502 free(mxcs); 503 return NULL; 504 } 505 506 cs = ret; 507 508 mxcs->slave.bus = bus; 509 mxcs->slave.cs = cs; 510 mxcs->base = spi_bases[bus]; 511 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; 512 513 ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); 514 if (ret) { 515 printf("mxc_spi: cannot setup SPI controller\n"); 516 free(mxcs); 517 return NULL; 518 } 519 return &mxcs->slave; 520 } 521 522 void spi_free_slave(struct spi_slave *slave) 523 { 524 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 525 526 free(mxcs); 527 } 528 529 int spi_claim_bus(struct spi_slave *slave) 530 { 531 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 532 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 533 534 reg_write(®s->rxdata, 1); 535 udelay(1); 536 reg_write(®s->ctrl, mxcs->ctrl_reg); 537 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); 538 reg_write(®s->intr, 0); 539 540 return 0; 541 } 542 543 void spi_release_bus(struct spi_slave *slave) 544 { 545 /* TODO: Shut the controller down */ 546 } 547