1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <malloc.h> 9 #include <spi.h> 10 #include <linux/errno.h> 11 #include <asm/io.h> 12 #include <asm/gpio.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/clock.h> 15 #include <asm/mach-imx/spi.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 #ifdef CONFIG_MX27 20 /* i.MX27 has a completely wrong register layout and register definitions in the 21 * datasheet, the correct one is in the Freescale's Linux driver */ 22 23 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ 24 "See linux mxc_spi driver from Freescale for details." 25 #endif 26 27 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs) 28 { 29 return -1; 30 } 31 32 #define OUT MXC_GPIO_DIRECTION_OUT 33 34 #define reg_read readl 35 #define reg_write(a, v) writel(v, a) 36 37 #if !defined(CONFIG_SYS_SPI_MXC_WAIT) 38 #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ 39 #endif 40 41 struct mxc_spi_slave { 42 struct spi_slave slave; 43 unsigned long base; 44 u32 ctrl_reg; 45 #if defined(MXC_ECSPI) 46 u32 cfg_reg; 47 #endif 48 int gpio; 49 int ss_pol; 50 unsigned int max_hz; 51 unsigned int mode; 52 struct gpio_desc ss; 53 }; 54 55 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) 56 { 57 return container_of(slave, struct mxc_spi_slave, slave); 58 } 59 60 static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs) 61 { 62 if (CONFIG_IS_ENABLED(DM_SPI)) { 63 dm_gpio_set_value(&mxcs->ss, 1); 64 } else { 65 if (mxcs->gpio > 0) 66 gpio_set_value(mxcs->gpio, mxcs->ss_pol); 67 } 68 } 69 70 static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs) 71 { 72 if (CONFIG_IS_ENABLED(DM_SPI)) { 73 dm_gpio_set_value(&mxcs->ss, 0); 74 } else { 75 if (mxcs->gpio > 0) 76 gpio_set_value(mxcs->gpio, !(mxcs->ss_pol)); 77 } 78 } 79 80 u32 get_cspi_div(u32 div) 81 { 82 int i; 83 84 for (i = 0; i < 8; i++) { 85 if (div <= (4 << i)) 86 return i; 87 } 88 return i; 89 } 90 91 #ifdef MXC_CSPI 92 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) 93 { 94 unsigned int ctrl_reg; 95 u32 clk_src; 96 u32 div; 97 unsigned int max_hz = mxcs->max_hz; 98 unsigned int mode = mxcs->mode; 99 100 clk_src = mxc_get_clock(MXC_CSPI_CLK); 101 102 div = DIV_ROUND_UP(clk_src, max_hz); 103 div = get_cspi_div(div); 104 105 debug("clk %d Hz, div %d, real clk %d Hz\n", 106 max_hz, div, clk_src / (4 << div)); 107 108 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | 109 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | 110 MXC_CSPICTRL_DATARATE(div) | 111 MXC_CSPICTRL_EN | 112 #ifdef CONFIG_MX35 113 MXC_CSPICTRL_SSCTL | 114 #endif 115 MXC_CSPICTRL_MODE; 116 117 if (mode & SPI_CPHA) 118 ctrl_reg |= MXC_CSPICTRL_PHA; 119 if (mode & SPI_CPOL) 120 ctrl_reg |= MXC_CSPICTRL_POL; 121 if (mode & SPI_CS_HIGH) 122 ctrl_reg |= MXC_CSPICTRL_SSPOL; 123 mxcs->ctrl_reg = ctrl_reg; 124 125 return 0; 126 } 127 #endif 128 129 #ifdef MXC_ECSPI 130 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) 131 { 132 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); 133 s32 reg_ctrl, reg_config; 134 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; 135 u32 pre_div = 0, post_div = 0; 136 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 137 unsigned int max_hz = mxcs->max_hz; 138 unsigned int mode = mxcs->mode; 139 140 /* 141 * Reset SPI and set all CSs to master mode, if toggling 142 * between slave and master mode we might see a glitch 143 * on the clock line 144 */ 145 reg_ctrl = MXC_CSPICTRL_MODE_MASK; 146 reg_write(®s->ctrl, reg_ctrl); 147 reg_ctrl |= MXC_CSPICTRL_EN; 148 reg_write(®s->ctrl, reg_ctrl); 149 150 if (clk_src > max_hz) { 151 pre_div = (clk_src - 1) / max_hz; 152 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */ 153 post_div = fls(pre_div); 154 if (post_div > 4) { 155 post_div -= 4; 156 if (post_div >= 16) { 157 printf("Error: no divider for the freq: %d\n", 158 max_hz); 159 return -1; 160 } 161 pre_div >>= post_div; 162 } else { 163 post_div = 0; 164 } 165 } 166 167 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); 168 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | 169 MXC_CSPICTRL_SELCHAN(cs); 170 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | 171 MXC_CSPICTRL_PREDIV(pre_div); 172 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | 173 MXC_CSPICTRL_POSTDIV(post_div); 174 175 if (mode & SPI_CS_HIGH) 176 ss_pol = 1; 177 178 if (mode & SPI_CPOL) { 179 sclkpol = 1; 180 sclkctl = 1; 181 } 182 183 if (mode & SPI_CPHA) 184 sclkpha = 1; 185 186 reg_config = reg_read(®s->cfg); 187 188 /* 189 * Configuration register setup 190 * The MX51 supports different setup for each SS 191 */ 192 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | 193 (ss_pol << (cs + MXC_CSPICON_SSPOL)); 194 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | 195 (sclkpol << (cs + MXC_CSPICON_POL)); 196 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) | 197 (sclkctl << (cs + MXC_CSPICON_CTL)); 198 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | 199 (sclkpha << (cs + MXC_CSPICON_PHA)); 200 201 debug("reg_ctrl = 0x%x\n", reg_ctrl); 202 reg_write(®s->ctrl, reg_ctrl); 203 debug("reg_config = 0x%x\n", reg_config); 204 reg_write(®s->cfg, reg_config); 205 206 /* save config register and control register */ 207 mxcs->ctrl_reg = reg_ctrl; 208 mxcs->cfg_reg = reg_config; 209 210 /* clear interrupt reg */ 211 reg_write(®s->intr, 0); 212 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 213 214 return 0; 215 } 216 #endif 217 218 int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen, 219 const u8 *dout, u8 *din, unsigned long flags) 220 { 221 int nbytes = DIV_ROUND_UP(bitlen, 8); 222 u32 data, cnt, i; 223 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 224 u32 ts; 225 int status; 226 227 debug("%s: bitlen %d dout 0x%x din 0x%x\n", 228 __func__, bitlen, (u32)dout, (u32)din); 229 230 mxcs->ctrl_reg = (mxcs->ctrl_reg & 231 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | 232 MXC_CSPICTRL_BITCOUNT(bitlen - 1); 233 234 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); 235 #ifdef MXC_ECSPI 236 reg_write(®s->cfg, mxcs->cfg_reg); 237 #endif 238 239 /* Clear interrupt register */ 240 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 241 242 /* 243 * The SPI controller works only with words, 244 * check if less than a word is sent. 245 * Access to the FIFO is only 32 bit 246 */ 247 if (bitlen % 32) { 248 data = 0; 249 cnt = (bitlen % 32) / 8; 250 if (dout) { 251 for (i = 0; i < cnt; i++) { 252 data = (data << 8) | (*dout++ & 0xFF); 253 } 254 } 255 debug("Sending SPI 0x%x\n", data); 256 257 reg_write(®s->txdata, data); 258 nbytes -= cnt; 259 } 260 261 data = 0; 262 263 while (nbytes > 0) { 264 data = 0; 265 if (dout) { 266 /* Buffer is not 32-bit aligned */ 267 if ((unsigned long)dout & 0x03) { 268 data = 0; 269 for (i = 0; i < 4; i++) 270 data = (data << 8) | (*dout++ & 0xFF); 271 } else { 272 data = *(u32 *)dout; 273 data = cpu_to_be32(data); 274 dout += 4; 275 } 276 } 277 debug("Sending SPI 0x%x\n", data); 278 reg_write(®s->txdata, data); 279 nbytes -= 4; 280 } 281 282 /* FIFO is written, now starts the transfer setting the XCH bit */ 283 reg_write(®s->ctrl, mxcs->ctrl_reg | 284 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); 285 286 ts = get_timer(0); 287 status = reg_read(®s->stat); 288 /* Wait until the TC (Transfer completed) bit is set */ 289 while ((status & MXC_CSPICTRL_TC) == 0) { 290 if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) { 291 printf("spi_xchg_single: Timeout!\n"); 292 return -1; 293 } 294 status = reg_read(®s->stat); 295 } 296 297 /* Transfer completed, clear any pending request */ 298 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 299 300 nbytes = DIV_ROUND_UP(bitlen, 8); 301 302 cnt = nbytes % 32; 303 304 if (bitlen % 32) { 305 data = reg_read(®s->rxdata); 306 cnt = (bitlen % 32) / 8; 307 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); 308 debug("SPI Rx unaligned: 0x%x\n", data); 309 if (din) { 310 memcpy(din, &data, cnt); 311 din += cnt; 312 } 313 nbytes -= cnt; 314 } 315 316 while (nbytes > 0) { 317 u32 tmp; 318 tmp = reg_read(®s->rxdata); 319 data = cpu_to_be32(tmp); 320 debug("SPI Rx: 0x%x 0x%x\n", tmp, data); 321 cnt = min_t(u32, nbytes, sizeof(data)); 322 if (din) { 323 memcpy(din, &data, cnt); 324 din += cnt; 325 } 326 nbytes -= cnt; 327 } 328 329 return 0; 330 331 } 332 333 static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs, 334 unsigned int bitlen, const void *dout, 335 void *din, unsigned long flags) 336 { 337 int n_bytes = DIV_ROUND_UP(bitlen, 8); 338 int n_bits; 339 int ret; 340 u32 blk_size; 341 u8 *p_outbuf = (u8 *)dout; 342 u8 *p_inbuf = (u8 *)din; 343 344 if (!mxcs) 345 return -EINVAL; 346 347 if (flags & SPI_XFER_BEGIN) 348 mxc_spi_cs_activate(mxcs); 349 350 while (n_bytes > 0) { 351 if (n_bytes < MAX_SPI_BYTES) 352 blk_size = n_bytes; 353 else 354 blk_size = MAX_SPI_BYTES; 355 356 n_bits = blk_size * 8; 357 358 ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0); 359 360 if (ret) 361 return ret; 362 if (dout) 363 p_outbuf += blk_size; 364 if (din) 365 p_inbuf += blk_size; 366 n_bytes -= blk_size; 367 } 368 369 if (flags & SPI_XFER_END) { 370 mxc_spi_cs_deactivate(mxcs); 371 } 372 373 return 0; 374 } 375 376 static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs) 377 { 378 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 379 int ret; 380 381 reg_write(®s->rxdata, 1); 382 udelay(1); 383 ret = spi_cfg_mxc(mxcs, cs); 384 if (ret) { 385 printf("mxc_spi: cannot setup SPI controller\n"); 386 return ret; 387 } 388 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); 389 reg_write(®s->intr, 0); 390 391 return 0; 392 } 393 394 #ifndef CONFIG_DM_SPI 395 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 396 void *din, unsigned long flags) 397 { 398 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 399 400 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags); 401 } 402 403 void spi_init(void) 404 { 405 } 406 407 /* 408 * Some SPI devices require active chip-select over multiple 409 * transactions, we achieve this using a GPIO. Still, the SPI 410 * controller has to be configured to use one of its own chipselects. 411 * To use this feature you have to implement board_spi_cs_gpio() to assign 412 * a gpio value for each cs (-1 if cs doesn't need to use gpio). 413 * You must use some unused on this SPI controller cs between 0 and 3. 414 */ 415 static int setup_cs_gpio(struct mxc_spi_slave *mxcs, 416 unsigned int bus, unsigned int cs) 417 { 418 int ret; 419 420 mxcs->gpio = board_spi_cs_gpio(bus, cs); 421 if (mxcs->gpio == -1) 422 return 0; 423 424 gpio_request(mxcs->gpio, "spi-cs"); 425 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); 426 if (ret) { 427 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); 428 return -EINVAL; 429 } 430 431 return 0; 432 } 433 434 static unsigned long spi_bases[] = { 435 MXC_SPI_BASE_ADDRESSES 436 }; 437 438 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 439 unsigned int max_hz, unsigned int mode) 440 { 441 struct mxc_spi_slave *mxcs; 442 int ret; 443 444 if (bus >= ARRAY_SIZE(spi_bases)) 445 return NULL; 446 447 if (max_hz == 0) { 448 printf("Error: desired clock is 0\n"); 449 return NULL; 450 } 451 452 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); 453 if (!mxcs) { 454 puts("mxc_spi: SPI Slave not allocated !\n"); 455 return NULL; 456 } 457 458 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; 459 460 ret = setup_cs_gpio(mxcs, bus, cs); 461 if (ret < 0) { 462 free(mxcs); 463 return NULL; 464 } 465 466 mxcs->base = spi_bases[bus]; 467 mxcs->max_hz = max_hz; 468 mxcs->mode = mode; 469 470 return &mxcs->slave; 471 } 472 473 void spi_free_slave(struct spi_slave *slave) 474 { 475 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 476 477 free(mxcs); 478 } 479 480 int spi_claim_bus(struct spi_slave *slave) 481 { 482 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 483 484 return mxc_spi_claim_bus_internal(mxcs, slave->cs); 485 } 486 487 void spi_release_bus(struct spi_slave *slave) 488 { 489 /* TODO: Shut the controller down */ 490 } 491 #else 492 493 static int mxc_spi_probe(struct udevice *bus) 494 { 495 struct mxc_spi_slave *plat = bus->platdata; 496 struct mxc_spi_slave *mxcs = dev_get_platdata(bus); 497 int node = dev_of_offset(bus); 498 const void *blob = gd->fdt_blob; 499 int ret; 500 501 if (gpio_request_by_name(bus, "cs-gpios", 0, &plat->ss, 502 GPIOD_IS_OUT)) { 503 dev_err(bus, "No cs-gpios property\n"); 504 return -EINVAL; 505 } 506 507 plat->base = devfdt_get_addr(bus); 508 if (plat->base == FDT_ADDR_T_NONE) 509 return -ENODEV; 510 511 ret = dm_gpio_set_value(&plat->ss, 0); 512 if (ret) { 513 dev_err(bus, "Setting cs error\n"); 514 return ret; 515 } 516 517 mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 518 20000000); 519 520 return 0; 521 } 522 523 static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen, 524 const void *dout, void *din, unsigned long flags) 525 { 526 struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent); 527 528 529 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags); 530 } 531 532 static int mxc_spi_claim_bus(struct udevice *dev) 533 { 534 struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent); 535 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 536 537 return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs); 538 } 539 540 static int mxc_spi_release_bus(struct udevice *dev) 541 { 542 return 0; 543 } 544 545 static int mxc_spi_set_speed(struct udevice *bus, uint speed) 546 { 547 /* Nothing to do */ 548 return 0; 549 } 550 551 static int mxc_spi_set_mode(struct udevice *bus, uint mode) 552 { 553 struct mxc_spi_slave *mxcs = dev_get_platdata(bus); 554 555 mxcs->mode = mode; 556 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; 557 558 return 0; 559 } 560 561 static const struct dm_spi_ops mxc_spi_ops = { 562 .claim_bus = mxc_spi_claim_bus, 563 .release_bus = mxc_spi_release_bus, 564 .xfer = mxc_spi_xfer, 565 .set_speed = mxc_spi_set_speed, 566 .set_mode = mxc_spi_set_mode, 567 }; 568 569 static const struct udevice_id mxc_spi_ids[] = { 570 { .compatible = "fsl,imx51-ecspi" }, 571 { } 572 }; 573 574 U_BOOT_DRIVER(mxc_spi) = { 575 .name = "mxc_spi", 576 .id = UCLASS_SPI, 577 .of_match = mxc_spi_ids, 578 .ops = &mxc_spi_ops, 579 .platdata_auto_alloc_size = sizeof(struct mxc_spi_slave), 580 .probe = mxc_spi_probe, 581 }; 582 #endif 583