1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #include <common.h> 22 #include <malloc.h> 23 #include <spi.h> 24 #include <asm/errno.h> 25 #include <asm/io.h> 26 #include <asm/gpio.h> 27 #include <asm/arch/imx-regs.h> 28 #include <asm/arch/clock.h> 29 30 #ifdef CONFIG_MX27 31 /* i.MX27 has a completely wrong register layout and register definitions in the 32 * datasheet, the correct one is in the Freescale's Linux driver */ 33 34 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ 35 "See linux mxc_spi driver from Freescale for details." 36 #endif 37 38 static unsigned long spi_bases[] = { 39 MXC_SPI_BASE_ADDRESSES 40 }; 41 42 #define OUT MXC_GPIO_DIRECTION_OUT 43 44 #define reg_read readl 45 #define reg_write(a, v) writel(v, a) 46 47 struct mxc_spi_slave { 48 struct spi_slave slave; 49 unsigned long base; 50 u32 ctrl_reg; 51 #if defined(MXC_ECSPI) 52 u32 cfg_reg; 53 #endif 54 int gpio; 55 int ss_pol; 56 }; 57 58 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) 59 { 60 return container_of(slave, struct mxc_spi_slave, slave); 61 } 62 63 void spi_cs_activate(struct spi_slave *slave) 64 { 65 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 66 if (mxcs->gpio > 0) 67 gpio_set_value(mxcs->gpio, mxcs->ss_pol); 68 } 69 70 void spi_cs_deactivate(struct spi_slave *slave) 71 { 72 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 73 if (mxcs->gpio > 0) 74 gpio_set_value(mxcs->gpio, 75 !(mxcs->ss_pol)); 76 } 77 78 u32 get_cspi_div(u32 div) 79 { 80 int i; 81 82 for (i = 0; i < 8; i++) { 83 if (div <= (4 << i)) 84 return i; 85 } 86 return i; 87 } 88 89 #ifdef MXC_CSPI 90 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 91 unsigned int max_hz, unsigned int mode) 92 { 93 unsigned int ctrl_reg; 94 u32 clk_src; 95 u32 div; 96 97 clk_src = mxc_get_clock(MXC_CSPI_CLK); 98 99 div = DIV_ROUND_UP(clk_src, max_hz); 100 div = get_cspi_div(div); 101 102 debug("clk %d Hz, div %d, real clk %d Hz\n", 103 max_hz, div, clk_src / (4 << div)); 104 105 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | 106 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | 107 MXC_CSPICTRL_DATARATE(div) | 108 MXC_CSPICTRL_EN | 109 #ifdef CONFIG_MX35 110 MXC_CSPICTRL_SSCTL | 111 #endif 112 MXC_CSPICTRL_MODE; 113 114 if (mode & SPI_CPHA) 115 ctrl_reg |= MXC_CSPICTRL_PHA; 116 if (mode & SPI_CPOL) 117 ctrl_reg |= MXC_CSPICTRL_POL; 118 if (mode & SPI_CS_HIGH) 119 ctrl_reg |= MXC_CSPICTRL_SSPOL; 120 mxcs->ctrl_reg = ctrl_reg; 121 122 return 0; 123 } 124 #endif 125 126 #ifdef MXC_ECSPI 127 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 128 unsigned int max_hz, unsigned int mode) 129 { 130 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); 131 s32 reg_ctrl, reg_config; 132 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, pre_div = 0, post_div = 0; 133 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 134 135 if (max_hz == 0) { 136 printf("Error: desired clock is 0\n"); 137 return -1; 138 } 139 140 /* 141 * Reset SPI and set all CSs to master mode, if toggling 142 * between slave and master mode we might see a glitch 143 * on the clock line 144 */ 145 reg_ctrl = MXC_CSPICTRL_MODE_MASK; 146 reg_write(®s->ctrl, reg_ctrl); 147 reg_ctrl |= MXC_CSPICTRL_EN; 148 reg_write(®s->ctrl, reg_ctrl); 149 150 if (clk_src > max_hz) { 151 pre_div = (clk_src - 1) / max_hz; 152 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */ 153 post_div = fls(pre_div); 154 if (post_div > 4) { 155 post_div -= 4; 156 if (post_div >= 16) { 157 printf("Error: no divider for the freq: %d\n", 158 max_hz); 159 return -1; 160 } 161 pre_div >>= post_div; 162 } else { 163 post_div = 0; 164 } 165 } 166 167 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); 168 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | 169 MXC_CSPICTRL_SELCHAN(cs); 170 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | 171 MXC_CSPICTRL_PREDIV(pre_div); 172 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | 173 MXC_CSPICTRL_POSTDIV(post_div); 174 175 /* We need to disable SPI before changing registers */ 176 reg_ctrl &= ~MXC_CSPICTRL_EN; 177 178 if (mode & SPI_CS_HIGH) 179 ss_pol = 1; 180 181 if (mode & SPI_CPOL) 182 sclkpol = 1; 183 184 if (mode & SPI_CPHA) 185 sclkpha = 1; 186 187 reg_config = reg_read(®s->cfg); 188 189 /* 190 * Configuration register setup 191 * The MX51 supports different setup for each SS 192 */ 193 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | 194 (ss_pol << (cs + MXC_CSPICON_SSPOL)); 195 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | 196 (sclkpol << (cs + MXC_CSPICON_POL)); 197 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | 198 (sclkpha << (cs + MXC_CSPICON_PHA)); 199 200 debug("reg_ctrl = 0x%x\n", reg_ctrl); 201 reg_write(®s->ctrl, reg_ctrl); 202 debug("reg_config = 0x%x\n", reg_config); 203 reg_write(®s->cfg, reg_config); 204 205 /* save config register and control register */ 206 mxcs->ctrl_reg = reg_ctrl; 207 mxcs->cfg_reg = reg_config; 208 209 /* clear interrupt reg */ 210 reg_write(®s->intr, 0); 211 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 212 213 return 0; 214 } 215 #endif 216 217 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, 218 const u8 *dout, u8 *din, unsigned long flags) 219 { 220 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 221 int nbytes = (bitlen + 7) / 8; 222 u32 data, cnt, i; 223 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 224 225 debug("%s: bitlen %d dout 0x%x din 0x%x\n", 226 __func__, bitlen, (u32)dout, (u32)din); 227 228 mxcs->ctrl_reg = (mxcs->ctrl_reg & 229 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | 230 MXC_CSPICTRL_BITCOUNT(bitlen - 1); 231 232 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); 233 #ifdef MXC_ECSPI 234 reg_write(®s->cfg, mxcs->cfg_reg); 235 #endif 236 237 /* Clear interrupt register */ 238 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 239 240 /* 241 * The SPI controller works only with words, 242 * check if less than a word is sent. 243 * Access to the FIFO is only 32 bit 244 */ 245 if (bitlen % 32) { 246 data = 0; 247 cnt = (bitlen % 32) / 8; 248 if (dout) { 249 for (i = 0; i < cnt; i++) { 250 data = (data << 8) | (*dout++ & 0xFF); 251 } 252 } 253 debug("Sending SPI 0x%x\n", data); 254 255 reg_write(®s->txdata, data); 256 nbytes -= cnt; 257 } 258 259 data = 0; 260 261 while (nbytes > 0) { 262 data = 0; 263 if (dout) { 264 /* Buffer is not 32-bit aligned */ 265 if ((unsigned long)dout & 0x03) { 266 data = 0; 267 for (i = 0; i < 4; i++) 268 data = (data << 8) | (*dout++ & 0xFF); 269 } else { 270 data = *(u32 *)dout; 271 data = cpu_to_be32(data); 272 } 273 dout += 4; 274 } 275 debug("Sending SPI 0x%x\n", data); 276 reg_write(®s->txdata, data); 277 nbytes -= 4; 278 } 279 280 /* FIFO is written, now starts the transfer setting the XCH bit */ 281 reg_write(®s->ctrl, mxcs->ctrl_reg | 282 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); 283 284 /* Wait until the TC (Transfer completed) bit is set */ 285 while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0) 286 ; 287 288 /* Transfer completed, clear any pending request */ 289 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 290 291 nbytes = (bitlen + 7) / 8; 292 293 cnt = nbytes % 32; 294 295 if (bitlen % 32) { 296 data = reg_read(®s->rxdata); 297 cnt = (bitlen % 32) / 8; 298 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); 299 debug("SPI Rx unaligned: 0x%x\n", data); 300 if (din) { 301 memcpy(din, &data, cnt); 302 din += cnt; 303 } 304 nbytes -= cnt; 305 } 306 307 while (nbytes > 0) { 308 u32 tmp; 309 tmp = reg_read(®s->rxdata); 310 data = cpu_to_be32(tmp); 311 debug("SPI Rx: 0x%x 0x%x\n", tmp, data); 312 cnt = min(nbytes, sizeof(data)); 313 if (din) { 314 memcpy(din, &data, cnt); 315 din += cnt; 316 } 317 nbytes -= cnt; 318 } 319 320 return 0; 321 322 } 323 324 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 325 void *din, unsigned long flags) 326 { 327 int n_bytes = (bitlen + 7) / 8; 328 int n_bits; 329 int ret; 330 u32 blk_size; 331 u8 *p_outbuf = (u8 *)dout; 332 u8 *p_inbuf = (u8 *)din; 333 334 if (!slave) 335 return -1; 336 337 if (flags & SPI_XFER_BEGIN) 338 spi_cs_activate(slave); 339 340 while (n_bytes > 0) { 341 if (n_bytes < MAX_SPI_BYTES) 342 blk_size = n_bytes; 343 else 344 blk_size = MAX_SPI_BYTES; 345 346 n_bits = blk_size * 8; 347 348 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); 349 350 if (ret) 351 return ret; 352 if (dout) 353 p_outbuf += blk_size; 354 if (din) 355 p_inbuf += blk_size; 356 n_bytes -= blk_size; 357 } 358 359 if (flags & SPI_XFER_END) { 360 spi_cs_deactivate(slave); 361 } 362 363 return 0; 364 } 365 366 void spi_init(void) 367 { 368 } 369 370 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) 371 { 372 int ret; 373 374 /* 375 * Some SPI devices require active chip-select over multiple 376 * transactions, we achieve this using a GPIO. Still, the SPI 377 * controller has to be configured to use one of its own chipselects. 378 * To use this feature you have to call spi_setup_slave() with 379 * cs = internal_cs | (gpio << 8), and you have to use some unused 380 * on this SPI controller cs between 0 and 3. 381 */ 382 if (cs > 3) { 383 mxcs->gpio = cs >> 8; 384 cs &= 3; 385 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); 386 if (ret) { 387 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); 388 return -EINVAL; 389 } 390 } else { 391 mxcs->gpio = -1; 392 } 393 394 return cs; 395 } 396 397 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 398 unsigned int max_hz, unsigned int mode) 399 { 400 struct mxc_spi_slave *mxcs; 401 int ret; 402 403 if (bus >= ARRAY_SIZE(spi_bases)) 404 return NULL; 405 406 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); 407 if (!mxcs) { 408 puts("mxc_spi: SPI Slave not allocated !\n"); 409 return NULL; 410 } 411 412 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; 413 414 ret = decode_cs(mxcs, cs); 415 if (ret < 0) { 416 free(mxcs); 417 return NULL; 418 } 419 420 cs = ret; 421 422 mxcs->base = spi_bases[bus]; 423 424 ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); 425 if (ret) { 426 printf("mxc_spi: cannot setup SPI controller\n"); 427 free(mxcs); 428 return NULL; 429 } 430 return &mxcs->slave; 431 } 432 433 void spi_free_slave(struct spi_slave *slave) 434 { 435 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 436 437 free(mxcs); 438 } 439 440 int spi_claim_bus(struct spi_slave *slave) 441 { 442 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 443 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 444 445 reg_write(®s->rxdata, 1); 446 udelay(1); 447 reg_write(®s->ctrl, mxcs->ctrl_reg); 448 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); 449 reg_write(®s->intr, 0); 450 451 return 0; 452 } 453 454 void spi_release_bus(struct spi_slave *slave) 455 { 456 /* TODO: Shut the controller down */ 457 } 458