xref: /openbmc/u-boot/drivers/spi/mxc_spi.c (revision b1e6c4c3)
1 /*
2  * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of
7  * the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17  * MA 02111-1307 USA
18  *
19  */
20 
21 #include <common.h>
22 #include <malloc.h>
23 #include <spi.h>
24 #include <asm/errno.h>
25 #include <asm/io.h>
26 #include <asm/gpio.h>
27 #include <asm/arch/imx-regs.h>
28 #include <asm/arch/clock.h>
29 
30 #ifdef CONFIG_MX27
31 /* i.MX27 has a completely wrong register layout and register definitions in the
32  * datasheet, the correct one is in the Freescale's Linux driver */
33 
34 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
35 "See linux mxc_spi driver from Freescale for details."
36 #endif
37 
38 static unsigned long spi_bases[] = {
39 	MXC_SPI_BASE_ADDRESSES
40 };
41 
42 #define OUT	MXC_GPIO_DIRECTION_OUT
43 
44 #define reg_read readl
45 #define reg_write(a, v) writel(v, a)
46 
47 struct mxc_spi_slave {
48 	struct spi_slave slave;
49 	unsigned long	base;
50 	u32		ctrl_reg;
51 #if defined(MXC_ECSPI)
52 	u32		cfg_reg;
53 #endif
54 	int		gpio;
55 	int		ss_pol;
56 };
57 
58 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
59 {
60 	return container_of(slave, struct mxc_spi_slave, slave);
61 }
62 
63 void spi_cs_activate(struct spi_slave *slave)
64 {
65 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
66 	if (mxcs->gpio > 0)
67 		gpio_set_value(mxcs->gpio, mxcs->ss_pol);
68 }
69 
70 void spi_cs_deactivate(struct spi_slave *slave)
71 {
72 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
73 	if (mxcs->gpio > 0)
74 		gpio_set_value(mxcs->gpio,
75 			      !(mxcs->ss_pol));
76 }
77 
78 u32 get_cspi_div(u32 div)
79 {
80 	int i;
81 
82 	for (i = 0; i < 8; i++) {
83 		if (div <= (4 << i))
84 			return i;
85 	}
86 	return i;
87 }
88 
89 #ifdef MXC_CSPI
90 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
91 		unsigned int max_hz, unsigned int mode)
92 {
93 	unsigned int ctrl_reg;
94 	u32 clk_src;
95 	u32 div;
96 
97 	clk_src = mxc_get_clock(MXC_CSPI_CLK);
98 
99 	div = DIV_ROUND_UP(clk_src, max_hz);
100 	div = get_cspi_div(div);
101 
102 	debug("clk %d Hz, div %d, real clk %d Hz\n",
103 		max_hz, div, clk_src / (4 << div));
104 
105 	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
106 		MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
107 		MXC_CSPICTRL_DATARATE(div) |
108 		MXC_CSPICTRL_EN |
109 #ifdef CONFIG_MX35
110 		MXC_CSPICTRL_SSCTL |
111 #endif
112 		MXC_CSPICTRL_MODE;
113 
114 	if (mode & SPI_CPHA)
115 		ctrl_reg |= MXC_CSPICTRL_PHA;
116 	if (mode & SPI_CPOL)
117 		ctrl_reg |= MXC_CSPICTRL_POL;
118 	if (mode & SPI_CS_HIGH)
119 		ctrl_reg |= MXC_CSPICTRL_SSPOL;
120 	mxcs->ctrl_reg = ctrl_reg;
121 
122 	return 0;
123 }
124 #endif
125 
126 #ifdef MXC_ECSPI
127 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
128 		unsigned int max_hz, unsigned int mode)
129 {
130 	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
131 	s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
132 	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
133 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
134 
135 	if (max_hz == 0) {
136 		printf("Error: desired clock is 0\n");
137 		return -1;
138 	}
139 
140 	/*
141 	 * Reset SPI and set all CSs to master mode, if toggling
142 	 * between slave and master mode we might see a glitch
143 	 * on the clock line
144 	 */
145 	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
146 	reg_write(&regs->ctrl, reg_ctrl);
147 	reg_ctrl |=  MXC_CSPICTRL_EN;
148 	reg_write(&regs->ctrl, reg_ctrl);
149 
150 	/*
151 	 * The following computation is taken directly from Freescale's code.
152 	 */
153 	if (clk_src > max_hz) {
154 		pre_div = DIV_ROUND_UP(clk_src, max_hz);
155 		if (pre_div > 16) {
156 			post_div = pre_div / 16;
157 			pre_div = 15;
158 		}
159 		if (post_div != 0) {
160 			for (i = 0; i < 16; i++) {
161 				if ((1 << i) >= post_div)
162 					break;
163 			}
164 			if (i == 16) {
165 				printf("Error: no divider for the freq: %d\n",
166 					max_hz);
167 				return -1;
168 			}
169 			post_div = i;
170 		}
171 	}
172 
173 	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
174 	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
175 		MXC_CSPICTRL_SELCHAN(cs);
176 	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
177 		MXC_CSPICTRL_PREDIV(pre_div);
178 	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
179 		MXC_CSPICTRL_POSTDIV(post_div);
180 
181 	/* We need to disable SPI before changing registers */
182 	reg_ctrl &= ~MXC_CSPICTRL_EN;
183 
184 	if (mode & SPI_CS_HIGH)
185 		ss_pol = 1;
186 
187 	if (mode & SPI_CPOL)
188 		sclkpol = 1;
189 
190 	if (mode & SPI_CPHA)
191 		sclkpha = 1;
192 
193 	reg_config = reg_read(&regs->cfg);
194 
195 	/*
196 	 * Configuration register setup
197 	 * The MX51 supports different setup for each SS
198 	 */
199 	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
200 		(ss_pol << (cs + MXC_CSPICON_SSPOL));
201 	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
202 		(sclkpol << (cs + MXC_CSPICON_POL));
203 	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
204 		(sclkpha << (cs + MXC_CSPICON_PHA));
205 
206 	debug("reg_ctrl = 0x%x\n", reg_ctrl);
207 	reg_write(&regs->ctrl, reg_ctrl);
208 	debug("reg_config = 0x%x\n", reg_config);
209 	reg_write(&regs->cfg, reg_config);
210 
211 	/* save config register and control register */
212 	mxcs->ctrl_reg = reg_ctrl;
213 	mxcs->cfg_reg = reg_config;
214 
215 	/* clear interrupt reg */
216 	reg_write(&regs->intr, 0);
217 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
218 
219 	return 0;
220 }
221 #endif
222 
223 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
224 	const u8 *dout, u8 *din, unsigned long flags)
225 {
226 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
227 	int nbytes = (bitlen + 7) / 8;
228 	u32 data, cnt, i;
229 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
230 
231 	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
232 		__func__, bitlen, (u32)dout, (u32)din);
233 
234 	mxcs->ctrl_reg = (mxcs->ctrl_reg &
235 		~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
236 		MXC_CSPICTRL_BITCOUNT(bitlen - 1);
237 
238 	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
239 #ifdef MXC_ECSPI
240 	reg_write(&regs->cfg, mxcs->cfg_reg);
241 #endif
242 
243 	/* Clear interrupt register */
244 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
245 
246 	/*
247 	 * The SPI controller works only with words,
248 	 * check if less than a word is sent.
249 	 * Access to the FIFO is only 32 bit
250 	 */
251 	if (bitlen % 32) {
252 		data = 0;
253 		cnt = (bitlen % 32) / 8;
254 		if (dout) {
255 			for (i = 0; i < cnt; i++) {
256 				data = (data << 8) | (*dout++ & 0xFF);
257 			}
258 		}
259 		debug("Sending SPI 0x%x\n", data);
260 
261 		reg_write(&regs->txdata, data);
262 		nbytes -= cnt;
263 	}
264 
265 	data = 0;
266 
267 	while (nbytes > 0) {
268 		data = 0;
269 		if (dout) {
270 			/* Buffer is not 32-bit aligned */
271 			if ((unsigned long)dout & 0x03) {
272 				data = 0;
273 				for (i = 0; i < 4; i++)
274 					data = (data << 8) | (*dout++ & 0xFF);
275 			} else {
276 				data = *(u32 *)dout;
277 				data = cpu_to_be32(data);
278 			}
279 			dout += 4;
280 		}
281 		debug("Sending SPI 0x%x\n", data);
282 		reg_write(&regs->txdata, data);
283 		nbytes -= 4;
284 	}
285 
286 	/* FIFO is written, now starts the transfer setting the XCH bit */
287 	reg_write(&regs->ctrl, mxcs->ctrl_reg |
288 		MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
289 
290 	/* Wait until the TC (Transfer completed) bit is set */
291 	while ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)
292 		;
293 
294 	/* Transfer completed, clear any pending request */
295 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
296 
297 	nbytes = (bitlen + 7) / 8;
298 
299 	cnt = nbytes % 32;
300 
301 	if (bitlen % 32) {
302 		data = reg_read(&regs->rxdata);
303 		cnt = (bitlen % 32) / 8;
304 		data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
305 		debug("SPI Rx unaligned: 0x%x\n", data);
306 		if (din) {
307 			memcpy(din, &data, cnt);
308 			din += cnt;
309 		}
310 		nbytes -= cnt;
311 	}
312 
313 	while (nbytes > 0) {
314 		u32 tmp;
315 		tmp = reg_read(&regs->rxdata);
316 		data = cpu_to_be32(tmp);
317 		debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
318 		cnt = min(nbytes, sizeof(data));
319 		if (din) {
320 			memcpy(din, &data, cnt);
321 			din += cnt;
322 		}
323 		nbytes -= cnt;
324 	}
325 
326 	return 0;
327 
328 }
329 
330 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
331 		void *din, unsigned long flags)
332 {
333 	int n_bytes = (bitlen + 7) / 8;
334 	int n_bits;
335 	int ret;
336 	u32 blk_size;
337 	u8 *p_outbuf = (u8 *)dout;
338 	u8 *p_inbuf = (u8 *)din;
339 
340 	if (!slave)
341 		return -1;
342 
343 	if (flags & SPI_XFER_BEGIN)
344 		spi_cs_activate(slave);
345 
346 	while (n_bytes > 0) {
347 		if (n_bytes < MAX_SPI_BYTES)
348 			blk_size = n_bytes;
349 		else
350 			blk_size = MAX_SPI_BYTES;
351 
352 		n_bits = blk_size * 8;
353 
354 		ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
355 
356 		if (ret)
357 			return ret;
358 		if (dout)
359 			p_outbuf += blk_size;
360 		if (din)
361 			p_inbuf += blk_size;
362 		n_bytes -= blk_size;
363 	}
364 
365 	if (flags & SPI_XFER_END) {
366 		spi_cs_deactivate(slave);
367 	}
368 
369 	return 0;
370 }
371 
372 void spi_init(void)
373 {
374 }
375 
376 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
377 {
378 	int ret;
379 
380 	/*
381 	 * Some SPI devices require active chip-select over multiple
382 	 * transactions, we achieve this using a GPIO. Still, the SPI
383 	 * controller has to be configured to use one of its own chipselects.
384 	 * To use this feature you have to call spi_setup_slave() with
385 	 * cs = internal_cs | (gpio << 8), and you have to use some unused
386 	 * on this SPI controller cs between 0 and 3.
387 	 */
388 	if (cs > 3) {
389 		mxcs->gpio = cs >> 8;
390 		cs &= 3;
391 		ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
392 		if (ret) {
393 			printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
394 			return -EINVAL;
395 		}
396 	} else {
397 		mxcs->gpio = -1;
398 	}
399 
400 	return cs;
401 }
402 
403 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
404 			unsigned int max_hz, unsigned int mode)
405 {
406 	struct mxc_spi_slave *mxcs;
407 	int ret;
408 
409 	if (bus >= ARRAY_SIZE(spi_bases))
410 		return NULL;
411 
412 	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
413 	if (!mxcs) {
414 		puts("mxc_spi: SPI Slave not allocated !\n");
415 		return NULL;
416 	}
417 
418 	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
419 
420 	ret = decode_cs(mxcs, cs);
421 	if (ret < 0) {
422 		free(mxcs);
423 		return NULL;
424 	}
425 
426 	cs = ret;
427 
428 	mxcs->base = spi_bases[bus];
429 
430 	ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
431 	if (ret) {
432 		printf("mxc_spi: cannot setup SPI controller\n");
433 		free(mxcs);
434 		return NULL;
435 	}
436 	return &mxcs->slave;
437 }
438 
439 void spi_free_slave(struct spi_slave *slave)
440 {
441 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
442 
443 	free(mxcs);
444 }
445 
446 int spi_claim_bus(struct spi_slave *slave)
447 {
448 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
449 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
450 
451 	reg_write(&regs->rxdata, 1);
452 	udelay(1);
453 	reg_write(&regs->ctrl, mxcs->ctrl_reg);
454 	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
455 	reg_write(&regs->intr, 0);
456 
457 	return 0;
458 }
459 
460 void spi_release_bus(struct spi_slave *slave)
461 {
462 	/* TODO: Shut the controller down */
463 }
464