1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <spi.h> 10 #include <asm/errno.h> 11 #include <asm/io.h> 12 #include <asm/gpio.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/clock.h> 15 #include <asm/imx-common/spi.h> 16 17 #ifdef CONFIG_MX27 18 /* i.MX27 has a completely wrong register layout and register definitions in the 19 * datasheet, the correct one is in the Freescale's Linux driver */ 20 21 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ 22 "See linux mxc_spi driver from Freescale for details." 23 #endif 24 25 static unsigned long spi_bases[] = { 26 MXC_SPI_BASE_ADDRESSES 27 }; 28 29 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs) 30 { 31 return -1; 32 } 33 34 #define OUT MXC_GPIO_DIRECTION_OUT 35 36 #define reg_read readl 37 #define reg_write(a, v) writel(v, a) 38 39 #if !defined(CONFIG_SYS_SPI_MXC_WAIT) 40 #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ 41 #endif 42 43 struct mxc_spi_slave { 44 struct spi_slave slave; 45 unsigned long base; 46 u32 ctrl_reg; 47 #if defined(MXC_ECSPI) 48 u32 cfg_reg; 49 #endif 50 int gpio; 51 int ss_pol; 52 }; 53 54 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) 55 { 56 return container_of(slave, struct mxc_spi_slave, slave); 57 } 58 59 void spi_cs_activate(struct spi_slave *slave) 60 { 61 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 62 if (mxcs->gpio > 0) 63 gpio_set_value(mxcs->gpio, mxcs->ss_pol); 64 } 65 66 void spi_cs_deactivate(struct spi_slave *slave) 67 { 68 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 69 if (mxcs->gpio > 0) 70 gpio_set_value(mxcs->gpio, 71 !(mxcs->ss_pol)); 72 } 73 74 u32 get_cspi_div(u32 div) 75 { 76 int i; 77 78 for (i = 0; i < 8; i++) { 79 if (div <= (4 << i)) 80 return i; 81 } 82 return i; 83 } 84 85 #ifdef MXC_CSPI 86 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 87 unsigned int max_hz, unsigned int mode) 88 { 89 unsigned int ctrl_reg; 90 u32 clk_src; 91 u32 div; 92 93 clk_src = mxc_get_clock(MXC_CSPI_CLK); 94 95 div = DIV_ROUND_UP(clk_src, max_hz); 96 div = get_cspi_div(div); 97 98 debug("clk %d Hz, div %d, real clk %d Hz\n", 99 max_hz, div, clk_src / (4 << div)); 100 101 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | 102 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | 103 MXC_CSPICTRL_DATARATE(div) | 104 MXC_CSPICTRL_EN | 105 #ifdef CONFIG_MX35 106 MXC_CSPICTRL_SSCTL | 107 #endif 108 MXC_CSPICTRL_MODE; 109 110 if (mode & SPI_CPHA) 111 ctrl_reg |= MXC_CSPICTRL_PHA; 112 if (mode & SPI_CPOL) 113 ctrl_reg |= MXC_CSPICTRL_POL; 114 if (mode & SPI_CS_HIGH) 115 ctrl_reg |= MXC_CSPICTRL_SSPOL; 116 mxcs->ctrl_reg = ctrl_reg; 117 118 return 0; 119 } 120 #endif 121 122 #ifdef MXC_ECSPI 123 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 124 unsigned int max_hz, unsigned int mode) 125 { 126 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); 127 s32 reg_ctrl, reg_config; 128 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; 129 u32 pre_div = 0, post_div = 0; 130 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 131 132 if (max_hz == 0) { 133 printf("Error: desired clock is 0\n"); 134 return -1; 135 } 136 137 /* 138 * Reset SPI and set all CSs to master mode, if toggling 139 * between slave and master mode we might see a glitch 140 * on the clock line 141 */ 142 reg_ctrl = MXC_CSPICTRL_MODE_MASK; 143 reg_write(®s->ctrl, reg_ctrl); 144 reg_ctrl |= MXC_CSPICTRL_EN; 145 reg_write(®s->ctrl, reg_ctrl); 146 147 if (clk_src > max_hz) { 148 pre_div = (clk_src - 1) / max_hz; 149 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */ 150 post_div = fls(pre_div); 151 if (post_div > 4) { 152 post_div -= 4; 153 if (post_div >= 16) { 154 printf("Error: no divider for the freq: %d\n", 155 max_hz); 156 return -1; 157 } 158 pre_div >>= post_div; 159 } else { 160 post_div = 0; 161 } 162 } 163 164 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); 165 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | 166 MXC_CSPICTRL_SELCHAN(cs); 167 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | 168 MXC_CSPICTRL_PREDIV(pre_div); 169 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | 170 MXC_CSPICTRL_POSTDIV(post_div); 171 172 /* We need to disable SPI before changing registers */ 173 reg_ctrl &= ~MXC_CSPICTRL_EN; 174 175 if (mode & SPI_CS_HIGH) 176 ss_pol = 1; 177 178 if (mode & SPI_CPOL) { 179 sclkpol = 1; 180 sclkctl = 1; 181 } 182 183 if (mode & SPI_CPHA) 184 sclkpha = 1; 185 186 reg_config = reg_read(®s->cfg); 187 188 /* 189 * Configuration register setup 190 * The MX51 supports different setup for each SS 191 */ 192 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | 193 (ss_pol << (cs + MXC_CSPICON_SSPOL)); 194 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | 195 (sclkpol << (cs + MXC_CSPICON_POL)); 196 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) | 197 (sclkctl << (cs + MXC_CSPICON_CTL)); 198 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | 199 (sclkpha << (cs + MXC_CSPICON_PHA)); 200 201 debug("reg_ctrl = 0x%x\n", reg_ctrl); 202 reg_write(®s->ctrl, reg_ctrl); 203 debug("reg_config = 0x%x\n", reg_config); 204 reg_write(®s->cfg, reg_config); 205 206 /* save config register and control register */ 207 mxcs->ctrl_reg = reg_ctrl; 208 mxcs->cfg_reg = reg_config; 209 210 /* clear interrupt reg */ 211 reg_write(®s->intr, 0); 212 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 213 214 return 0; 215 } 216 #endif 217 218 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, 219 const u8 *dout, u8 *din, unsigned long flags) 220 { 221 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 222 int nbytes = DIV_ROUND_UP(bitlen, 8); 223 u32 data, cnt, i; 224 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 225 u32 ts; 226 int status; 227 228 debug("%s: bitlen %d dout 0x%x din 0x%x\n", 229 __func__, bitlen, (u32)dout, (u32)din); 230 231 mxcs->ctrl_reg = (mxcs->ctrl_reg & 232 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | 233 MXC_CSPICTRL_BITCOUNT(bitlen - 1); 234 235 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); 236 #ifdef MXC_ECSPI 237 reg_write(®s->cfg, mxcs->cfg_reg); 238 #endif 239 240 /* Clear interrupt register */ 241 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 242 243 /* 244 * The SPI controller works only with words, 245 * check if less than a word is sent. 246 * Access to the FIFO is only 32 bit 247 */ 248 if (bitlen % 32) { 249 data = 0; 250 cnt = (bitlen % 32) / 8; 251 if (dout) { 252 for (i = 0; i < cnt; i++) { 253 data = (data << 8) | (*dout++ & 0xFF); 254 } 255 } 256 debug("Sending SPI 0x%x\n", data); 257 258 reg_write(®s->txdata, data); 259 nbytes -= cnt; 260 } 261 262 data = 0; 263 264 while (nbytes > 0) { 265 data = 0; 266 if (dout) { 267 /* Buffer is not 32-bit aligned */ 268 if ((unsigned long)dout & 0x03) { 269 data = 0; 270 for (i = 0; i < 4; i++) 271 data = (data << 8) | (*dout++ & 0xFF); 272 } else { 273 data = *(u32 *)dout; 274 data = cpu_to_be32(data); 275 dout += 4; 276 } 277 } 278 debug("Sending SPI 0x%x\n", data); 279 reg_write(®s->txdata, data); 280 nbytes -= 4; 281 } 282 283 /* FIFO is written, now starts the transfer setting the XCH bit */ 284 reg_write(®s->ctrl, mxcs->ctrl_reg | 285 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); 286 287 ts = get_timer(0); 288 status = reg_read(®s->stat); 289 /* Wait until the TC (Transfer completed) bit is set */ 290 while ((status & MXC_CSPICTRL_TC) == 0) { 291 if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) { 292 printf("spi_xchg_single: Timeout!\n"); 293 return -1; 294 } 295 status = reg_read(®s->stat); 296 } 297 298 /* Transfer completed, clear any pending request */ 299 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 300 301 nbytes = DIV_ROUND_UP(bitlen, 8); 302 303 cnt = nbytes % 32; 304 305 if (bitlen % 32) { 306 data = reg_read(®s->rxdata); 307 cnt = (bitlen % 32) / 8; 308 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); 309 debug("SPI Rx unaligned: 0x%x\n", data); 310 if (din) { 311 memcpy(din, &data, cnt); 312 din += cnt; 313 } 314 nbytes -= cnt; 315 } 316 317 while (nbytes > 0) { 318 u32 tmp; 319 tmp = reg_read(®s->rxdata); 320 data = cpu_to_be32(tmp); 321 debug("SPI Rx: 0x%x 0x%x\n", tmp, data); 322 cnt = min(nbytes, sizeof(data)); 323 if (din) { 324 memcpy(din, &data, cnt); 325 din += cnt; 326 } 327 nbytes -= cnt; 328 } 329 330 return 0; 331 332 } 333 334 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 335 void *din, unsigned long flags) 336 { 337 int n_bytes = DIV_ROUND_UP(bitlen, 8); 338 int n_bits; 339 int ret; 340 u32 blk_size; 341 u8 *p_outbuf = (u8 *)dout; 342 u8 *p_inbuf = (u8 *)din; 343 344 if (!slave) 345 return -1; 346 347 if (flags & SPI_XFER_BEGIN) 348 spi_cs_activate(slave); 349 350 while (n_bytes > 0) { 351 if (n_bytes < MAX_SPI_BYTES) 352 blk_size = n_bytes; 353 else 354 blk_size = MAX_SPI_BYTES; 355 356 n_bits = blk_size * 8; 357 358 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); 359 360 if (ret) 361 return ret; 362 if (dout) 363 p_outbuf += blk_size; 364 if (din) 365 p_inbuf += blk_size; 366 n_bytes -= blk_size; 367 } 368 369 if (flags & SPI_XFER_END) { 370 spi_cs_deactivate(slave); 371 } 372 373 return 0; 374 } 375 376 void spi_init(void) 377 { 378 } 379 380 /* 381 * Some SPI devices require active chip-select over multiple 382 * transactions, we achieve this using a GPIO. Still, the SPI 383 * controller has to be configured to use one of its own chipselects. 384 * To use this feature you have to implement board_spi_cs_gpio() to assign 385 * a gpio value for each cs (-1 if cs doesn't need to use gpio). 386 * You must use some unused on this SPI controller cs between 0 and 3. 387 */ 388 static int setup_cs_gpio(struct mxc_spi_slave *mxcs, 389 unsigned int bus, unsigned int cs) 390 { 391 int ret; 392 393 mxcs->gpio = board_spi_cs_gpio(bus, cs); 394 if (mxcs->gpio == -1) 395 return 0; 396 397 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); 398 if (ret) { 399 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); 400 return -EINVAL; 401 } 402 403 return 0; 404 } 405 406 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 407 unsigned int max_hz, unsigned int mode) 408 { 409 struct mxc_spi_slave *mxcs; 410 int ret; 411 412 if (bus >= ARRAY_SIZE(spi_bases)) 413 return NULL; 414 415 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); 416 if (!mxcs) { 417 puts("mxc_spi: SPI Slave not allocated !\n"); 418 return NULL; 419 } 420 421 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; 422 423 ret = setup_cs_gpio(mxcs, bus, cs); 424 if (ret < 0) { 425 free(mxcs); 426 return NULL; 427 } 428 429 mxcs->base = spi_bases[bus]; 430 431 ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); 432 if (ret) { 433 printf("mxc_spi: cannot setup SPI controller\n"); 434 free(mxcs); 435 return NULL; 436 } 437 return &mxcs->slave; 438 } 439 440 void spi_free_slave(struct spi_slave *slave) 441 { 442 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 443 444 free(mxcs); 445 } 446 447 int spi_claim_bus(struct spi_slave *slave) 448 { 449 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 450 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 451 452 reg_write(®s->rxdata, 1); 453 udelay(1); 454 reg_write(®s->ctrl, mxcs->ctrl_reg); 455 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); 456 reg_write(®s->intr, 0); 457 458 return 0; 459 } 460 461 void spi_release_bus(struct spi_slave *slave) 462 { 463 /* TODO: Shut the controller down */ 464 } 465