xref: /openbmc/u-boot/drivers/spi/mxc_spi.c (revision a3b36c84)
1 /*
2  * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <dm.h>
9 #include <malloc.h>
10 #include <spi.h>
11 #include <linux/errno.h>
12 #include <asm/io.h>
13 #include <asm/gpio.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/mach-imx/spi.h>
17 
18 DECLARE_GLOBAL_DATA_PTR;
19 
20 #ifdef CONFIG_MX27
21 /* i.MX27 has a completely wrong register layout and register definitions in the
22  * datasheet, the correct one is in the Freescale's Linux driver */
23 
24 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
25 "See linux mxc_spi driver from Freescale for details."
26 #endif
27 
28 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
29 {
30 	return -1;
31 }
32 
33 #define OUT	MXC_GPIO_DIRECTION_OUT
34 
35 #define reg_read readl
36 #define reg_write(a, v) writel(v, a)
37 
38 #if !defined(CONFIG_SYS_SPI_MXC_WAIT)
39 #define CONFIG_SYS_SPI_MXC_WAIT		(CONFIG_SYS_HZ/100)	/* 10 ms */
40 #endif
41 
42 struct mxc_spi_slave {
43 	struct spi_slave slave;
44 	unsigned long	base;
45 	u32		ctrl_reg;
46 #if defined(MXC_ECSPI)
47 	u32		cfg_reg;
48 #endif
49 	int		gpio;
50 	int		ss_pol;
51 	unsigned int	max_hz;
52 	unsigned int	mode;
53 	struct gpio_desc ss;
54 };
55 
56 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
57 {
58 	return container_of(slave, struct mxc_spi_slave, slave);
59 }
60 
61 static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
62 {
63 	if (CONFIG_IS_ENABLED(DM_SPI)) {
64 		dm_gpio_set_value(&mxcs->ss, mxcs->ss_pol);
65 	} else {
66 		if (mxcs->gpio > 0)
67 			gpio_set_value(mxcs->gpio, mxcs->ss_pol);
68 	}
69 }
70 
71 static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
72 {
73 	if (CONFIG_IS_ENABLED(DM_SPI)) {
74 		dm_gpio_set_value(&mxcs->ss, !(mxcs->ss_pol));
75 	} else {
76 		if (mxcs->gpio > 0)
77 			gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
78 	}
79 }
80 
81 u32 get_cspi_div(u32 div)
82 {
83 	int i;
84 
85 	for (i = 0; i < 8; i++) {
86 		if (div <= (4 << i))
87 			return i;
88 	}
89 	return i;
90 }
91 
92 #ifdef MXC_CSPI
93 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
94 {
95 	unsigned int ctrl_reg;
96 	u32 clk_src;
97 	u32 div;
98 	unsigned int max_hz = mxcs->max_hz;
99 	unsigned int mode = mxcs->mode;
100 
101 	clk_src = mxc_get_clock(MXC_CSPI_CLK);
102 
103 	div = DIV_ROUND_UP(clk_src, max_hz);
104 	div = get_cspi_div(div);
105 
106 	debug("clk %d Hz, div %d, real clk %d Hz\n",
107 		max_hz, div, clk_src / (4 << div));
108 
109 	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
110 		MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
111 		MXC_CSPICTRL_DATARATE(div) |
112 		MXC_CSPICTRL_EN |
113 #ifdef CONFIG_MX35
114 		MXC_CSPICTRL_SSCTL |
115 #endif
116 		MXC_CSPICTRL_MODE;
117 
118 	if (mode & SPI_CPHA)
119 		ctrl_reg |= MXC_CSPICTRL_PHA;
120 	if (mode & SPI_CPOL)
121 		ctrl_reg |= MXC_CSPICTRL_POL;
122 	if (mode & SPI_CS_HIGH)
123 		ctrl_reg |= MXC_CSPICTRL_SSPOL;
124 	mxcs->ctrl_reg = ctrl_reg;
125 
126 	return 0;
127 }
128 #endif
129 
130 #ifdef MXC_ECSPI
131 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
132 {
133 	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
134 	s32 reg_ctrl, reg_config;
135 	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
136 	u32 pre_div = 0, post_div = 0;
137 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
138 	unsigned int max_hz = mxcs->max_hz;
139 	unsigned int mode = mxcs->mode;
140 
141 	/*
142 	 * Reset SPI and set all CSs to master mode, if toggling
143 	 * between slave and master mode we might see a glitch
144 	 * on the clock line
145 	 */
146 	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
147 	reg_write(&regs->ctrl, reg_ctrl);
148 	reg_ctrl |=  MXC_CSPICTRL_EN;
149 	reg_write(&regs->ctrl, reg_ctrl);
150 
151 	if (clk_src > max_hz) {
152 		pre_div = (clk_src - 1) / max_hz;
153 		/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
154 		post_div = fls(pre_div);
155 		if (post_div > 4) {
156 			post_div -= 4;
157 			if (post_div >= 16) {
158 				printf("Error: no divider for the freq: %d\n",
159 					max_hz);
160 				return -1;
161 			}
162 			pre_div >>= post_div;
163 		} else {
164 			post_div = 0;
165 		}
166 	}
167 
168 	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
169 	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
170 		MXC_CSPICTRL_SELCHAN(cs);
171 	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
172 		MXC_CSPICTRL_PREDIV(pre_div);
173 	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
174 		MXC_CSPICTRL_POSTDIV(post_div);
175 
176 	if (mode & SPI_CS_HIGH)
177 		ss_pol = 1;
178 
179 	if (mode & SPI_CPOL) {
180 		sclkpol = 1;
181 		sclkctl = 1;
182 	}
183 
184 	if (mode & SPI_CPHA)
185 		sclkpha = 1;
186 
187 	reg_config = reg_read(&regs->cfg);
188 
189 	/*
190 	 * Configuration register setup
191 	 * The MX51 supports different setup for each SS
192 	 */
193 	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
194 		(ss_pol << (cs + MXC_CSPICON_SSPOL));
195 	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
196 		(sclkpol << (cs + MXC_CSPICON_POL));
197 	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
198 		(sclkctl << (cs + MXC_CSPICON_CTL));
199 	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
200 		(sclkpha << (cs + MXC_CSPICON_PHA));
201 
202 	debug("reg_ctrl = 0x%x\n", reg_ctrl);
203 	reg_write(&regs->ctrl, reg_ctrl);
204 	debug("reg_config = 0x%x\n", reg_config);
205 	reg_write(&regs->cfg, reg_config);
206 
207 	/* save config register and control register */
208 	mxcs->ctrl_reg = reg_ctrl;
209 	mxcs->cfg_reg = reg_config;
210 
211 	/* clear interrupt reg */
212 	reg_write(&regs->intr, 0);
213 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
214 
215 	return 0;
216 }
217 #endif
218 
219 int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
220 	const u8 *dout, u8 *din, unsigned long flags)
221 {
222 	int nbytes = DIV_ROUND_UP(bitlen, 8);
223 	u32 data, cnt, i;
224 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
225 	u32 ts;
226 	int status;
227 
228 	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
229 		__func__, bitlen, (u32)dout, (u32)din);
230 
231 	mxcs->ctrl_reg = (mxcs->ctrl_reg &
232 		~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
233 		MXC_CSPICTRL_BITCOUNT(bitlen - 1);
234 
235 	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
236 #ifdef MXC_ECSPI
237 	reg_write(&regs->cfg, mxcs->cfg_reg);
238 #endif
239 
240 	/* Clear interrupt register */
241 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
242 
243 	/*
244 	 * The SPI controller works only with words,
245 	 * check if less than a word is sent.
246 	 * Access to the FIFO is only 32 bit
247 	 */
248 	if (bitlen % 32) {
249 		data = 0;
250 		cnt = (bitlen % 32) / 8;
251 		if (dout) {
252 			for (i = 0; i < cnt; i++) {
253 				data = (data << 8) | (*dout++ & 0xFF);
254 			}
255 		}
256 		debug("Sending SPI 0x%x\n", data);
257 
258 		reg_write(&regs->txdata, data);
259 		nbytes -= cnt;
260 	}
261 
262 	data = 0;
263 
264 	while (nbytes > 0) {
265 		data = 0;
266 		if (dout) {
267 			/* Buffer is not 32-bit aligned */
268 			if ((unsigned long)dout & 0x03) {
269 				data = 0;
270 				for (i = 0; i < 4; i++)
271 					data = (data << 8) | (*dout++ & 0xFF);
272 			} else {
273 				data = *(u32 *)dout;
274 				data = cpu_to_be32(data);
275 				dout += 4;
276 			}
277 		}
278 		debug("Sending SPI 0x%x\n", data);
279 		reg_write(&regs->txdata, data);
280 		nbytes -= 4;
281 	}
282 
283 	/* FIFO is written, now starts the transfer setting the XCH bit */
284 	reg_write(&regs->ctrl, mxcs->ctrl_reg |
285 		MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
286 
287 	ts = get_timer(0);
288 	status = reg_read(&regs->stat);
289 	/* Wait until the TC (Transfer completed) bit is set */
290 	while ((status & MXC_CSPICTRL_TC) == 0) {
291 		if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
292 			printf("spi_xchg_single: Timeout!\n");
293 			return -1;
294 		}
295 		status = reg_read(&regs->stat);
296 	}
297 
298 	/* Transfer completed, clear any pending request */
299 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
300 
301 	nbytes = DIV_ROUND_UP(bitlen, 8);
302 
303 	cnt = nbytes % 32;
304 
305 	if (bitlen % 32) {
306 		data = reg_read(&regs->rxdata);
307 		cnt = (bitlen % 32) / 8;
308 		data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
309 		debug("SPI Rx unaligned: 0x%x\n", data);
310 		if (din) {
311 			memcpy(din, &data, cnt);
312 			din += cnt;
313 		}
314 		nbytes -= cnt;
315 	}
316 
317 	while (nbytes > 0) {
318 		u32 tmp;
319 		tmp = reg_read(&regs->rxdata);
320 		data = cpu_to_be32(tmp);
321 		debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
322 		cnt = min_t(u32, nbytes, sizeof(data));
323 		if (din) {
324 			memcpy(din, &data, cnt);
325 			din += cnt;
326 		}
327 		nbytes -= cnt;
328 	}
329 
330 	return 0;
331 
332 }
333 
334 static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
335 				 unsigned int bitlen, const void *dout,
336 				 void *din, unsigned long flags)
337 {
338 	int n_bytes = DIV_ROUND_UP(bitlen, 8);
339 	int n_bits;
340 	int ret;
341 	u32 blk_size;
342 	u8 *p_outbuf = (u8 *)dout;
343 	u8 *p_inbuf = (u8 *)din;
344 
345 	if (!mxcs)
346 		return -EINVAL;
347 
348 	if (flags & SPI_XFER_BEGIN)
349 		mxc_spi_cs_activate(mxcs);
350 
351 	while (n_bytes > 0) {
352 		if (n_bytes < MAX_SPI_BYTES)
353 			blk_size = n_bytes;
354 		else
355 			blk_size = MAX_SPI_BYTES;
356 
357 		n_bits = blk_size * 8;
358 
359 		ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
360 
361 		if (ret)
362 			return ret;
363 		if (dout)
364 			p_outbuf += blk_size;
365 		if (din)
366 			p_inbuf += blk_size;
367 		n_bytes -= blk_size;
368 	}
369 
370 	if (flags & SPI_XFER_END) {
371 		mxc_spi_cs_deactivate(mxcs);
372 	}
373 
374 	return 0;
375 }
376 
377 static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
378 {
379 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
380 	int ret;
381 
382 	reg_write(&regs->rxdata, 1);
383 	udelay(1);
384 	ret = spi_cfg_mxc(mxcs, cs);
385 	if (ret) {
386 		printf("mxc_spi: cannot setup SPI controller\n");
387 		return ret;
388 	}
389 	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
390 	reg_write(&regs->intr, 0);
391 
392 	return 0;
393 }
394 
395 #ifndef CONFIG_DM_SPI
396 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
397 		void *din, unsigned long flags)
398 {
399 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
400 
401 	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
402 }
403 
404 void spi_init(void)
405 {
406 }
407 
408 /*
409  * Some SPI devices require active chip-select over multiple
410  * transactions, we achieve this using a GPIO. Still, the SPI
411  * controller has to be configured to use one of its own chipselects.
412  * To use this feature you have to implement board_spi_cs_gpio() to assign
413  * a gpio value for each cs (-1 if cs doesn't need to use gpio).
414  * You must use some unused on this SPI controller cs between 0 and 3.
415  */
416 static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
417 			 unsigned int bus, unsigned int cs)
418 {
419 	int ret;
420 
421 	mxcs->gpio = board_spi_cs_gpio(bus, cs);
422 	if (mxcs->gpio == -1)
423 		return 0;
424 
425 	gpio_request(mxcs->gpio, "spi-cs");
426 	ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
427 	if (ret) {
428 		printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
429 		return -EINVAL;
430 	}
431 
432 	return 0;
433 }
434 
435 static unsigned long spi_bases[] = {
436 	MXC_SPI_BASE_ADDRESSES
437 };
438 
439 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
440 			unsigned int max_hz, unsigned int mode)
441 {
442 	struct mxc_spi_slave *mxcs;
443 	int ret;
444 
445 	if (bus >= ARRAY_SIZE(spi_bases))
446 		return NULL;
447 
448 	if (max_hz == 0) {
449 		printf("Error: desired clock is 0\n");
450 		return NULL;
451 	}
452 
453 	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
454 	if (!mxcs) {
455 		puts("mxc_spi: SPI Slave not allocated !\n");
456 		return NULL;
457 	}
458 
459 	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
460 
461 	ret = setup_cs_gpio(mxcs, bus, cs);
462 	if (ret < 0) {
463 		free(mxcs);
464 		return NULL;
465 	}
466 
467 	mxcs->base = spi_bases[bus];
468 	mxcs->max_hz = max_hz;
469 	mxcs->mode = mode;
470 
471 	return &mxcs->slave;
472 }
473 
474 void spi_free_slave(struct spi_slave *slave)
475 {
476 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
477 
478 	free(mxcs);
479 }
480 
481 int spi_claim_bus(struct spi_slave *slave)
482 {
483 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
484 
485 	return mxc_spi_claim_bus_internal(mxcs, slave->cs);
486 }
487 
488 void spi_release_bus(struct spi_slave *slave)
489 {
490 	/* TODO: Shut the controller down */
491 }
492 #else
493 
494 static int mxc_spi_probe(struct udevice *bus)
495 {
496 	struct mxc_spi_slave *plat = bus->platdata;
497 	struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
498 	int node = dev_of_offset(bus);
499 	const void *blob = gd->fdt_blob;
500 	int ret;
501 
502 	if (gpio_request_by_name(bus, "cs-gpios", 0, &plat->ss,
503 				 GPIOD_IS_OUT)) {
504 		dev_err(bus, "No cs-gpios property\n");
505 		return -EINVAL;
506 	}
507 
508 	plat->base = dev_get_addr(bus);
509 	if (plat->base == FDT_ADDR_T_NONE)
510 		return -ENODEV;
511 
512 	ret = dm_gpio_set_value(&plat->ss, !(mxcs->ss_pol));
513 	if (ret) {
514 		dev_err(bus, "Setting cs error\n");
515 		return ret;
516 	}
517 
518 	mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
519 				      20000000);
520 
521 	return 0;
522 }
523 
524 static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
525 		const void *dout, void *din, unsigned long flags)
526 {
527 	struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
528 
529 
530 	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
531 }
532 
533 static int mxc_spi_claim_bus(struct udevice *dev)
534 {
535 	struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
536 	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
537 
538 	return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
539 }
540 
541 static int mxc_spi_release_bus(struct udevice *dev)
542 {
543 	return 0;
544 }
545 
546 static int mxc_spi_set_speed(struct udevice *bus, uint speed)
547 {
548 	/* Nothing to do */
549 	return 0;
550 }
551 
552 static int mxc_spi_set_mode(struct udevice *bus, uint mode)
553 {
554 	struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
555 
556 	mxcs->mode = mode;
557 	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
558 
559 	return 0;
560 }
561 
562 static const struct dm_spi_ops mxc_spi_ops = {
563 	.claim_bus	= mxc_spi_claim_bus,
564 	.release_bus	= mxc_spi_release_bus,
565 	.xfer		= mxc_spi_xfer,
566 	.set_speed	= mxc_spi_set_speed,
567 	.set_mode	= mxc_spi_set_mode,
568 };
569 
570 static const struct udevice_id mxc_spi_ids[] = {
571 	{ .compatible = "fsl,imx51-ecspi" },
572 	{ }
573 };
574 
575 U_BOOT_DRIVER(mxc_spi) = {
576 	.name	= "mxc_spi",
577 	.id	= UCLASS_SPI,
578 	.of_match = mxc_spi_ids,
579 	.ops	= &mxc_spi_ops,
580 	.platdata_auto_alloc_size = sizeof(struct mxc_spi_slave),
581 	.probe	= mxc_spi_probe,
582 };
583 #endif
584